A5086357798- 3D IC and TSV technologies
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices
- Advanced Neural Network Applications
- VLSI and Analog Circuit Testing
- Advancements in Photolithography Techniques
- Interconnection Networks and Systems
- Semiconductor Lasers and Optical Devices
- Machine Learning and ELM
- Radiation Detection and Scintillator Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Radiation Effects in Electronics
- Particle Detector Development and Performance
- Advancements in Semiconductor Devices and Circuit Design
Georgia Institute of Technology
2019-2024
A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than a monolithic flow. This approach expands access to large catalog off-the-shelf intellectual properties (IPs), allows them, and enables heterogeneous blocks different technologies. In this article, we present highly integrated flow that encompasses architecture, circuit, package build simulate...
A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paper we present a highly-integrated flow that encompasses architecture, circuit, and package to build simulate heterogeneous designs. We chipletize each by adding logical protocol translators physical interface modules. These chiplets are placed/routed on silicon interposer next. Our models then used calculate PPA signal/power integrity of the overall system. space exploration study our tool shows...
Resistive random access memory (RRAM)-based compute-in-memory architecture helps overcome the bottleneck caused by large transactions in convolutional neural network (CNN) accelerators. However, their deployment using 2-D IC technology faces challenges, as today's RRAM cells remain at legacy nodes above 20 nm due to high programming voltages. Besides, power-hungry analog-to-digital converter (ADC) units limit throughput of In this article, we present first-ever heterogeneous (multiple nodes)...
In this paper, we show that true 3D placement approaches, enhanced with reinforcement learning, can offer further PPA improvements over pseudo-3D approaches. To accomplish goal, integrate an academic engine into a commercial-grade physical design flow, creating ART-3D flow (Analytical Placement Reinforced Parameter Tuning-based flow). We use learning (RL) framework to find optimized parameter settings of the for given netlist and perform high-quality placement. then efficient optimization...
Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits (ICs) implementation flows. It transforms 2-D netlists into by performing tier assignment for each design instance, which directly impacts power, performance, and area (PPA) metrics final full-chip designs. However, current state-of-the-art approach named bin-based min-cut algorithm has fundamental flaws that lead to severe drawbacks, such as timing degradation, routing overhead, redundant...
Monolithic 3-D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic intertier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility designing circuits compared to conventional through silicon via (TSV)-based architectures. This article presents comprehensive design test techniques for emerging M3D-enabled systems.
Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of conventional through-silicon-via (TSV) and provides significant performance uplift power reduction. However, ultra-dense interconnects impose challenges during physical design on how to best utilize them. Besides, unique low-temperature fabrication process M3D requires dedicated design-for-test mechanisms verify reliability chip. In this article, we provide in-depth analysis these test...
Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most intensive applications. This has found wide-spread adoption in accelerating neural networks for machine learning Utilizing crossbar architecture with emerging non-volatile memories (eNVM) such as dense resistive random access memory (RRAM) or phase change (PCRAM), various forms can be implemented to greatly reduce power increase on chip capacity. However,...
D Place and Route (P&R) flows either involve true-3D placement algorithms or use commercial 2D tools to transform a design into 3D design. Irrespective of the nature placers, several parameters in these affect quality final designs. Different parameter settings work well with different circuits, it is impossible manually tune them for particular circuit. Automated approaches involving reinforcement learning have been shown adapt learn create trained models. However, their effectiveness...
This work identifies the architectural and design scaling limits of 2-D flexible interconnect deep neural network (DNN) accelerators addresses them with 3-D ICs. We demonstrate how up a baseline accelerator in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$X/Y$ </tex-math></inline-formula> dimension fails vertical stacking effectively overcomes failure. designed multitier that are...
In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool is based on commercial 2D tools smart ways to extend them conduct M3D simulation. We provide a post-route optimization flow, which exploits the full potential of underlying process kit (PDK) power, performance area (PPA) optimization. also IR-drop thermal analysis designs improve reliability. To enhance testability our designs,...
This paper presents 3DNN-Xplorer, the first machine learning (ML)-based framework for predicting performance of heterogeneous 3D DNN accelerators. Our ML frame-work facilitates design space exploration accelerators with a 2-tier compute-on-memory configuration, considering physical factors. encompasses four distinct integration styles, combining 28nm and 16nm technology nodes both compute memory tiers. Using extrapolation techniques models trained on 16, 32, 64 PE accelerator configurations,...
The 2-D CMOS process technology scaling may have reached its pinnacle, yet it is not feasible to manufacture all computing elements at lower technological nodes. This has opened a new branch of chip designing that allows chiplets on different nodes be integrated into single package using interposers, the passive interconnection mediums. However, establishing high-frequency communication over an entirely layer one significant design challenges 2.5-D systems. In this article, we present robust...
One of the advantages 3D IC technology is its ability to integrate different devices such as CMOS, SRAM, and RRAM, or multiple nodes single onto a chip due presence tiers. This create heterogeneous ICs finds wide range applications, from improving processor performance by integrating better memory technologies building compute-in-memory support advanced machine learning algorithms. paper discusses current trends future directions for physical design ICs. We summarize various optimization...
Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most intensive applications. This has found wide-spread adoption in accelerating neural networks for machine learning Utilizing crossbar architecture with emerging non-volatile memories (eNVM) such as dense resistive random access memory (RRAM) or phase change (PCRAM), various forms can be implemented to greatly reduce power increase on chip capacity. However,...
Carbon nanotube FETs (CNFETs) are emerging as an alternative to silicon devices for next-generation computing systems. However, imperfect carbon deposition during CNFET fabrication can lead the formation of difficult-to-etch CNT aggregates in active layer. These form parasitic CNFETs (para-FETs) that modulated by adjoining gate contacts or back-end-of-line metal layers, thereby forming conditional shorts and stuck-at faults. We show even weak (parametric) para-FETs a degraded static noise...