A5081243379- Radio Frequency Integrated Circuit Design
- Microwave Engineering and Waveguides
- Analog and Mixed-Signal Circuit Design
- Advanced Power Amplifier Design
- GaN-based semiconductor devices and materials
- Advancements in PLL and VCO Technologies
- Bluetooth and Wireless Communication Technologies
- Energy Harvesting in Wireless Networks
- Wireless Body Area Networks
- VLSI and Analog Circuit Testing
- Electromagnetic Compatibility and Noise Suppression
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Quantum Structures and Devices
- Electrostatic Discharge in Electronics
- Wireless Networks and Protocols
Universidad de Las Palmas de Gran Canaria
2020-2025
The design of transformers, a key component radio frequency integrated circuits (RFICs), is traditionally carried out through an iterative process involving extensive electromagnetic simulations. While kits (PDKs) offer tools based on interpolation or fitting equations to simplify parameter estimation, these are restricted standard geometries, leaving designers manually simulate and optimize custom designs. This approach inefficient resource intensive. paper proposes automated generate...
The development of wake-up receivers (WuR) has recently received a lot interest from both academia and industry researchers, primarily because their major impact on the improvement performance wireless sensor networks (WSNs). In this paper, we present three different radiofrequency envelope detection (RFED) based WuRs operating at 868 MHz industrial, scientific medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components...
This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using gm/ID methodology. The Ka-band LNA achieves very power consumption only 1.98 mW andis first time approach is applied at such high frequency. circuit suitable for applications with central frequency 28 GHz, as intended to operate n257 band defined by 3GPP 5G new radio (NR) specification. proposed cascode uses methodology an RF/MW scenario exploit...
A 1.4-dB Noise Figure (NF) four-stage K-band Monolithic Microwave Integrated Circuit (MMIC) Low-Noise Amplifier (LNA) in UMS 100 nm GaAs pHEMT technology is presented. The proposed circuit designed to cover the 5G New Release n258 frequency band (24.25-27.58 GHz). Momentum EM post-layout simulations reveal achieves a minimum NF of 1.3 dB, maximum gain 34 |S11| better than -10 dB from 23 GHz 29 GHz, P1dB -18 dBm and an OIP3 24.5 dBm. LNA draws total current 59.1 mA 2 V DC supply results chip...
The implementation of a 0.38 V K-band low-power fully differential low-noise amplifier (LNA) in 45 nm silicon-on-insulator (SOI) process is presented. proposed architecture employs two-stage approach with transformer-based interstage matching networks to minimize circuit area. LNA covers the frequency range from 20.3 24.1 GHz, it achieves noise figure (NF) as low 2.2 dB, and gain 12.9 power consumption 11.7 mW DC supply very compact area (0.15 mm2) excluding pads. Non-linearity simulations...
Wireless sensor network (WSN) applications are under extensive research and development due to the need interconnect devices with each other. To reduce latency while keeping very low power consumption, implementation of a wake-up receiver (WuR) is particular interest. In WuR implementations, meeting high performance metrics design challenge, obtention high-sensitivity, data rate, low-power-consumption WuRs not straightforward procedure. The focus our proposals centered on consumption area...
In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs CC-based approach to obtain input matching without the need for bulky inductances, allowing broadband performance with very small area used. NC technique applied by subtracting transistor’s noise contribution output and achieves figure (NF) reduction from 4.8 dB 3.2 dB. LNA implemented in UMC 65-nm process occupies an of only 160 × 80 μm2. It stable...
This paper presents a methodology to design wideband radio frequency variable gain amplifier (RF-VGA) in low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). main feature of this is the input match along with reduced NF (5.5–9.6 dB) and, authors’ knowledge, lowest die footprint reported (62 × 44 μm2 area). implementation RF-VGA CCCII allows without need passive elements. Due nature circuit, when...
This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use receive phased arrays the gateways of major low Earth orbit (LEO) constellations that operate 17.8 to 20.2 GHz frequency range. proposed uses four variable gain amplifiers (VGA) are active at any given time switched generate quadrants. Compared conventional architectures, this structure more produces double output amplitude. offers 6-bit...