In this letter, we have investigated experimentally, for the first time, feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. situ material features high uniform-doping concentration, facilitating fabrication process. The developed JL device exhibits desirable electrostatic performance in terms higher ON/OFF current ratio...

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance a subthreshold swing 240 mV/dec on/off current ratio >; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> . Moreover, JL device shows 23 times increase in on-state at gate overdrive 4 V as compared conventional control...

A very simple and low-cost scheme is proposed for fabricating thin-film transistors with poly-Si nanowire (NW) channels. In this scheme, the NW channel formed by cleverly employing sidewall spacer technique. addition, genuinely exposed to environment after formation in new scheme. This unique feature, together its simplicity low-cost, makes approach suitable applications manufacturing of bio-logic sensing devices. Good device performance demonstrated letter.

This study showcases the use of ion-beam-assisted deposition for fabricating p-type SnO thin films at room temperature, which reveals crucial links between Hall mobility and lattice disorder, hole concentration relative content interstitial oxygen.

Abstract We study the influences of plasma hydrogenation on operation a novel poly-Si thin-film transistor (TFT) featuring T-shaped gate (T-gate), air spacers, and lightly doped drain (LDD). The treatments were done in commercial chamber with high density (AMAT Centura 5200, Applied Materials Inc.). results show that threshold voltage can be reduced, while field-effect mobility subthreshold swing greatly improved just half hour. Besides, evolution trends above parameters for T-gate device...

p-type SnO thin-film transistors (TFTs) using a nominally symmetrical double-gated (DG) structure were studied in this letter. The top and bottom gates can be biased independently (single-gated mode) or jointly to switch the device (DG mode). For latter operation, it is shown that ON current, subthreshold swing, OFF-state current of TFT are all improved as compared with operations when only one two biased. As operated under DG mode, field-effect mobility 6.54 cm <sup...

We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers Si3N4. A combination lithographic patterning, sidewall spacers, selfassembled growth was used for fabrication. The core experimental approach is based on selective oxidation poly-SiGe spacer islands located at specially designed included-angle locations Si3N4/Si-trenches. By adjusting...

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on passivation oxide employed to induce sheet of carriers in channel offset region located between active underneath main gate. The thus allows ambipolar operation by simply switching polarity bias applied field plate. contrast conventional SBTFT that suffers from high GIDL...

A novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in fabrication. In implementation of MILC process, it shown that arrangement seeding window plays an important role affecting resulting structure. this regard, asymmetric arrangement, i.e., locating on only one two channel sides preferred. When RTA combined,...

In this work we report the observation and characterization of a hysteresis phenomenon in transfer characteristics n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such is observed devices with fully depleted channel not treated hydrogen-related anneal. The origin identified to be related electron trapping detrapping processes associated deep-level traps grain boundaries poly-Si channel.

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive good control over performance variability. From C-V characterization, the ionized dopant concentration is determined be around 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm...

In this study, the effects of different reactants, namely, , and on nucleation deposition polycrystalline silicon‐germanium films oxide surface in an ultrahigh vacuum chemical vapor reactor were explored. The results show that addition tends to retard process poly while is preferential for adsorbing surface. These lead incubation duration depending kind reactants used. On films, it observed Ge incorporation only slightly related substrate type, but mode much from epitaxial growth Si(100)....

The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared conventional planar devices having self-aligned source/drain, the new show an improved on-current per unit width and better control over short effects. major conduction mechanism off-state leakage identified as gate-induced drain leakage, it closely related to source/drain implant condition unique device structure.

Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices fabricated simple methods without resorting to costly lithographic tools processes. The trigated show a low subthreshold swing (SS) around 100 mV/dec on/off current ratio higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . results clearly indicate the effectiveness MG...

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels two independent gates. The independently controllable gates allow higher flexibility in device operation provide a unique insight into conduction mechanism device. Our results indicate that dramatic performance enhancement feasible when thickness channel sufficiently thin, structure are operating simultaneously.

A method was developed to fabricate ZnO thin-film transistors (TFTs) with submicrometer channel length. In this scheme, mature process techniques are used form a suspending hardmask bridge on the wafer surface, which enables subsequent construction of TFT by sequential deposition gate oxide, layer, and Al source/drain contacts. Excellent electrical characteristics were demonstrated fabricated TFTs that show high ON/OFF current ratio , low subthreshold swing (89 mV/decade), field-effect...

In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-semiconductor (LDMOS) transistors. multifinger layout, the drain contact region was designed to be wider than channel region. The increases equivalent drift width reduce resistance and suppress quasi-saturation effect. We found that wide-drain LDMOS devices have lower on-resistance, higher cutoff frequency, maximum oscillation better power performances standard ones.

Over the past decade, SnO has been considered a promising p-type oxide semiconductor. However, achieving high mobility in fabrication of films is still highly dependent on post-annealing procedure, which often used to make SnO, due its metastable nature, readily convertible SnO2 and/or intermediate phases. This paper demonstrates fully room-temperature SnOx thin using ion-beam-assisted deposition. technique offers independent control between ion density, via ion-gun anode current and oxygen...

Thin-film transistors with poly-Si nanowire (NW) channels enhanced by metal-induced lateral crystallization (MILC) are reported. The new device features a side-gate self-aligned NW abutting the sidewalls of gate structure. By adopting MILC technique, crystallinity is greatly enhanced, compared to those formed solid-phase crystallization. As result, electrical performance devices could be significantly in terms reduced subthreshold swing and threshold voltage as well improved field-effect mobility.

A film profile engineering (FPE) concept which utilizes the unique features of various deposition tools to tailor and optimize deposited films was demonstrated with fabricated ZnO TFTs. By implementing PR trimming technique, high performance devices L <; 100 nm can be readily achieved.

In this study, we derive an analytical model of electric potential a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On basis model, subthreshold current and swing can be calculated. Threshold voltage roll-off also estimated with forms derived using above model. The calculated results potential, threshold are all in good agreement technology computer aided design (TCAD) simulation. proposed paper may help development...