Benjamin Richstein

ORCID: 0000-0003-1120-5426
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About
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Research Areas
  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Ferroelectric and Negative Capacitance Devices
  • Semiconductor materials and interfaces
  • Quantum and electron transport phenomena
  • Nanowire Synthesis and Applications
  • Semiconductor Quantum Structures and Devices
  • Gas Sensing Nanomaterials and Sensors
  • Advanced Memory and Neural Computing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Analytical Chemistry and Sensors
  • Electrochemical Analysis and Applications

RWTH Aachen University
2021-2025

Institute of Semiconductor Physics
2025

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks the improved electrostatics by scaled 3D GAA structure, close ideal transfer characteristics obtained at both RT K a sharp switching. Benefiting less defects in created implantation into silicide (IIS) process, band tail effects neutral scattering suppressed. Therefore, provide very low subthreshold swing SS 3.4...

10.1109/led.2022.3185781 article EN IEEE Electron Device Letters 2022-06-23

Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The quest for high-density, energy-efficient memories continues, with memory solutions still unclear. We present a Cryogenic Capacitorless Random Access Memory (C2RAM) cell using advanced Si technology, which enhances storage density through its scalability multistate capability. Remarkably, the C2RAM maintains over decade extended...

10.1021/acs.nanolett.4c05855 article EN cc-by Nano Letters 2025-04-13

Miniaturized electrolyte–insulator–semiconductor capacitors (EISCAPs) with ultrathin gate insulators have been studied in terms of their pH‐sensitive sensor characteristics: three different EISCAP systems consisting Al–p‐Si–Ta 2 O 5 (5 nm), Al–p‐Si–Si 3 N 4 (1 or nm)–Ta and Al–p‐Si–SiO (3.6 nm) layer structures are characterized buffer solution pH values by means capacitance–voltage constant capacitance method. The SiO Si deposited rapid thermal oxidation nitridation, respectively, whereas...

10.1002/pssa.202100660 article EN physica status solidi (a) 2022-01-22

In this work, we study experimentally the impact of different gate dielectric stacks on subthreshold behavior cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates off-state MOSFETs it turns out that at temperatures an appropriately thin, grown layer combination with a high-k counteracts saturation inverse slope and inflection phenomena. As result, steep strongly improved are demonstrated.

10.1109/led.2022.3217314 article EN IEEE Electron Device Letters 2022-11-03

We investigate the operation of dual-gate reconfigurable field-effect transistor (RFET) in programgate at drain (PGAD) and program-gate source (PGAS) configurations. To this end, silicon nanowire (SiNW) FETs are fabricated based on anisotropic wet chemical etching nickel silicidation yielding silicide-SiNW Schottky junctions drain. Whereas PGAD-configuration ambipolar is suppressed, switching deteriorated due to injection through a Schottky-barrier. Operating RFET PGAS configuration yields...

10.1109/ted.2021.3081527 article EN cc-by IEEE Transactions on Electron Devices 2021-05-28

Herein, cryogenic field‐effect transistors (FETs) are discussed. In particular, the saturation of subthreshold swing due to band tailing is studied. It shown with simulations and experiments that engineering oxide‐channel interfaces a strong increase gate oxide capacitance effective in improving switching behavior device. The implication scaling on power consumption devices investigated, too. Furthermore, an alternative for conventional doping Based synchrotron X‐Ray absorption spectroscopy...

10.1002/pssa.202300069 article EN cc-by-nc-nd physica status solidi (a) 2023-04-08

Problems with doping in nanoscale devices or low temperature applications are widely known. Our approach to replace the degenerate source/drain (S/D)-contacts is silicon nitride interface engineering. We measured Schottky diodes and MOSFETs very thin layers between metal. Al/SiN/p-Si show Fermi level depinning increasing SiN thickness. The diode fabricated rapid thermal nitridation at 900 ∘C reaches theoretical value of barrier conduction band ΦSB,n=0.2 eV. As a result, contact resistivity...

10.3390/micro1020017 article EN cc-by Micro 2021-11-21

Abstract In this roadmap we consider the status and challenges of technologies that use properties a rectifying metal-semiconductor interface, known as Schottky barrier, an asset for device functionality. We discuss source gated transistors, which allow excellent electronic characteristics low power, frequency environmentally friendly circuits. Also considered are reconfigurable field effect where presence two or more independent gate electrodes can be used to program different...

10.1088/2399-1984/ad92d1 article EN cc-by Nano Futures 2024-11-14

Abstract Efficient computing in cryogenic environments, encompassing classical von Neumann architectures, advanced quantum and neuromorphic systems, holds the potential to revolutionize big data processing. As demand for high storage density energy-efficient memories grows, absence of a clear solution memory remains challenge. Here, we present capacitorless Random Access Memory (C 2 RAM) utilizing Si technology. This innovation is positioned reshape computing, with its scalability capacity...

10.21203/rs.3.rs-3300928/v1 preprint EN cc-by Research Square (Research Square) 2023-10-17

The performance of metal-oxide field-effect tran-sistors is studied at cryogenic temperatures. Several approaches to reduce disorder-induced band-tailing and thus improve the switching behavior MOSFETs are discussed.

10.1109/nmdc57951.2023.10343713 article EN 2023-10-22

The present paper studies with experiment and simulation a number of measures that improve current cryogenic MOSFETs to enable the device be operated at very low supply voltages.

10.1109/snw56633.2022.9953898 article EN 2022-06-11
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