This paper presents a comparison between swarm intelligence (SI) techniques; namely Particle Swarm Optimization and Ant Colony Optimization, to solve analog circuit sizing problems. Performances in terms of optimum quality computing time both algorithms are checked via two applications that consist optimizing performances CMOS second generation current conveyor (CCII), an operational amplifier (Op-Amp).

This work focuses on the use of substitution modeling techniques and their combination with metaheuristics for rapid optimal sizing (not only) CMOS analog circuits. The case radial basis function model particle swarm optimization metaheuristic is considered. objective to show advantages such metamodeling inside an loop. We consider two circuits (four functions), we that approach allows obtaining sizing, similarly conventional in-loop technique but within a reduced computation time.

Particle swarm optimization (PSO) has shown to be an efficient, robust and simple algorithm. Recently, the mono-objective version of PSO algorithm was adapted used optimize only one performance RF circuits, mainly voltage gain low noise amplifiers. In this work, we propose more than function LNAs while satisfying imposed inherent constraints. We deal with generating Pareto front linking two conflicting performances a LNA, namely figure. The adopted idea consists using symbolic expressions...

The accuracy of high-frequency models passive RF devices, e.g., inductors or transformers, presents one the most challenging problems for integrated circuits. Accuracy limitations lead designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. first is based on segmented model approach, in which each device segment characterized a lumped element model. second technique generation surrogate from simulation set...

Multi-objective metaheuristics are over and again used by analog designers. Pareto fronts linking conflicting parameters usually generated using different optimisation techniques. Conclusions on these generally made in a subjective manner; no performance measures used! In this paper we deal with the use of two metrics, namely C-metric hypervolume indicator. The simulation-based technique is to generate non-dominated set points fronts. Two current mode circuits considered: conventional...

In this paper, we investigate the Optimizing Operational Transconductance Amplifiers through constrained Particle Swarm Optimization (PSO). We optimize folded cascode OTA performances, namely static gain, transition frequency, common mode rejection ratio (CMRR) and positive power-supply (PSRR). A comparaison with two other optimization methods shows good reached performances. The optimized circuit is used to design a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This work deals with the application of Kriging technique for accurate modeling analog circuits, namely, a CMOS second generation current conveyor, and voltage follower. Three types correlation functions are used this purpose: Spline, Gaussian Exponential Correlation functions. A comparative study is given. Two metrics used; Root Mean Square Error Maximum Absolute Error. Obtained results show that function provides better regarding accuracy constructed models, when compared to other

Frequently used approaches to solve discrete multivariable optimisation problems consist of computing solutions using a continuous technique. Then, heuristics, the variables are rounded-off their nearest available values obtain solution. Indeed, in many engineering problems, and particularly analogue circuit design, component values, such as geometric dimensions transistors, number fingers an integrated capacitor or turns inductor, cannot be chosen arbitrarily since they have obey some...

In this paper we consider the use of a new Kriging metamodeling technique for efficient global optimization analog circuits. It is based on socalled expected improvement criterion enhancement considered performance model. The efficiency approach, regarding to accuracy and computation time, showcased via an example optimal sizing CMOS operational transconductance amplifier. A comparative study with performances conventional in-loop technique, where particle swarm metaheuristic used as core...

Low-voltage low-power (LVLP) circuit design and optimization is a hard time-consuming task. In this study, we are interested in the application of newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models circuits’ performances were constructed then used within metaheuristic-based kernel order maximize sizing. The JAYA algorithm was for purpose. Three topologies CMOS current conveyors (CCII) considered showcase approach. achieved compared those...

Abstract This paper aims to make a trade‐off between performance and robustness in stochastic control systems with probabilistic uncertainties. For this purpose, we develop surrogate‐based robust simulation‐optimization approach for tuning analyzing the sensitivity of controllers. Kriging surrogate is combined design optimization construct model class dual response surfaces. Randomness simulation experiments due uncertainty analyzed through bootstrapping technique by computing confidence...

This brief proposes a novel multi-objective heuristic. It is transformation of mono-objective heuristic into one by addition an archive and some non dominance computing routines. Performances the proposed are demonstrated thru test functions. An application to optimal sizing class AB second generation CMOS current conveyor presented. Comparison with NSGA-II given.

In analog circuit sizing and optimization, both (meta)modeling metaheuristic-based techniques are gaining a lot of attention designers due to the advantages they offer when compared equation-based approach in-loop optimization technique. A metamodel is generally used as performance evaluator within routine. Both aforementioned techniques, i.e. metamodeling metaheuristic based intrinsically stochastic processes. They on random exploration design space. However, `random number' generator that...

In this paper, three meta heuristics are investigated to optimize analog circuit; namely genetic algorithms, particle swarm optimization and simulated annealing. A particular interest is given the of performances current conveyors. SPICE Simulation results show viability reached optimal results.

In this article we deal with the optimal sizing of low-noise amplifiers (LNAs) using newly proposed metamodeling techniques. The main objective is to construct metamodels performances LNAs (namely, third intercept point (IIP3), scattering parameters (Sij), and noise figure (NF)) use them inside an optimization kernel for maximizing circuits’ performances. kriging surrogate modelling technique used constructing these models. particle swarm (PSO) considered as metaheuristic. Two CMOS are...

The goal of this paper is to present a comparison among three known metaheuristics: Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Simulated Annealing (SA). For the comparison, design an LC - Voltage Controlled Oscillator (LC-VCO) considered, where minimization both VCO phase noise power consumption envisaged. objective find algorithm yielding best solution. validity solution obtained with each metaheuristic checked against HSPICE/RF simulation results. Robustness checks for...

In this brief, we deal with the generation of Pareto front for multi-objective analog circuit sizing optimization. The main idea proposed work consists using metamodels considered performances to generate set nondominated solutions. These models serve as evaluators. They offer several advantages, mainly their high precision reproducing real behavior performances, and very rapid evaluation, when compared counterpart, i.e. in-loop-based technique. Multiobjective particle swarm optimization...

In this paper, we consider the use of a new parallel efficient global optimization algorithm based on pseudo expected improvement (PEI) criterion, for optimal design analog circuits. A comparison with conventional (EGO) is presented. We show, via two circuit designs that proposed approach gives same sizing but within reduced computing time.