A5100780345- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies
- VLSI and Analog Circuit Testing
- Organic Electronics and Photovoltaics
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Radio Frequency Integrated Circuit Design
- Analytical Chemistry and Sensors
- Distributed and Parallel Computing Systems
- Conducting polymers and applications
- Semiconductor Lasers and Optical Devices
- Power Line Communications and Noise
- Advanced Memory and Neural Computing
- Plasma Diagnostics and Applications
- Internet of Things and Social Network Interactions
- Wireless Communication Networks Research
- Granular flow and fluidized beds
- Engineering Applied Research
- Thin-Film Transistor Technologies
- Electronic Packaging and Soldering Technologies
- Organic Light-Emitting Diodes Research
- Industrial Technology and Control Systems
- Optical Wireless Communication Technologies
- Advancements in Solid Oxide Fuel Cells
Sogang University
2023-2025
Hongik University
2023-2024
University of Seoul
2022-2023
Samsung (South Korea)
2007-2022
Korea Institute of Science & Technology Information
2017
Korea Electric Power Corporation (South Korea)
2014
Hanwha Techwin (South Korea)
2011
Pusan National University
2011
Kookmin University
2009-2010
Chonnam National University
2004
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of parallel single-ended signaling, power consumption I/O, supply noise, and crosstalk. Both DBI AC DC modes are combined single circuit eliminating feedback path conventional while achieving high-speed operation. The proposed uses analog majority voter insensitive mismatch for small area delay. R <sub...
To optimize the hydrogen content in a -IGZO TFTs, hafnium oxide (HfO 2 ) passivation via atomic layer deposition (ALD) and subsequent annealing were used. As result, AC stress stability was improved, reducing I on degradation rate from 69% to 9%.
Resistive random-access memory (RRAM) has been explored to implement neuromorphic systems accelerate neural networks. In this study, an RRAM crossbar array using parylene C (PPXC) as both a resistive switching layer and substrate was fabricated. PPXC is flexible transparent polymer with excellent chemical stability biocompatibility. We studied PPXC-based devices Ti/PPX-C/Cu Cu/PPX-C/Ti structures. Devices the structure offer stable electrical mechanical characteristics, such low set voltage...
Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up 6Gb/s. To maintain the speed increase, GDDR5 specification shifts from GDDR3/4 with respect forwarded clocking, data training write and read de-skewing, clock training, channel-error detection, bank group coding. This work tackles challenges such as jitter signal integrity.
The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb with a per-bit trainable single-ended decision feedback equalizer (DFE), reference impedance (ZQ)-coded transmitter, and phase-locked loop (PLL)-less clocking I/O speed by process. Furthermore, this optimizes clock- power-domain crossings adopts split-die architecture improve signal integrity (SI). operates 16 Gb/s/pin 1.15 V...
Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although GDDR5X can operate 12Gb/s [3] by increasing the burst length (BL) from 8 to 16, a degradation in system performance data granularity of 64B is seen. The I/O specification, using PLL clocking that additionally causes jitter, has not changed much compared GDDR5. To overcome these issues, GDDR6 introduced dual...
Until now, thermally activated delayed fluorescence (TADF) materials based on bridged boron-based acceptors have been primarily developed as dopants. However, in this study, we synthesized and characterized multifunctional deep-blue TADF materials─t-OBO-DMAC t-OBO-DPAC─using combination with dimethylacridine or diphenylacridine donors. These serve both dopants hosts. Theoretical calculations experimentally measured photophysical properties of t-OBO-DMAC reveal a smaller singlet–triplet...
Mobile systems for 5G communications and emerging technologies, such as advanced driver assistance system (ADAS), augmented reality (AR), artificial intelligence (AI), demand high-density, high-speed, low-power DRAM.LPDDR5 has played an important role in systems, by offering continuous improvements memory density (8, 12, 16Gb) speed (up to 8.5Gb/s) [1, 2, 3].LPDDR5X new high-speed enabling features: per-pin DFE training, pre-emphasis DQ driver, receiver offset calibration a read duty-cycle...
The anthracene derivative, 2MIQ-NPA , exhibits a high-lying reverse intersystem crossing process, diverging from El-Sayed rule. In the blue OLED utilizing exciton utilization efficiency reaches 64.3%, surpassing theoretical limit.
We compare measured and calculated electron-energy-loss phonon spectra of ultrathin films Ni grown on Cu(001) to determine the interlayer spacings layers. find a small (\ensuremath{\sim}4.6%) expansion in surface volume film at two four monolayers. Data modes along \ensuremath{\Gamma}\ifmmode\bar\else\textasciimacron\fi{} M\ifmmode\bar\else\textasciimacron\fi{} X\ifmmode\bar\else\textasciimacron\fi{} directions are for different thicknesses film, comparison between dispersions show...
A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation 68mV. dual duty-cycle corrector proposed average duty error, tuning added the auto-calibration of driver termination impedance.
Spiking neural networks (SNNs) have been researched as an alternative to reduce the gap with human brain in terms of energy efficiency, due their inherent spare event‐driven characteristics from a hardware implementation perspective. However, they still face significant challenges learning, compared artificial (ANNs). Recently, several algorithms developed narrow performance between SNNs and ANNs, including features spiking neurons that can information loss membrane potential. Inspired by...
The integration of MEMS, IDTs and required microelectronics conformal antennas to realize programmable, robust low cost passive microsensors suitable for many military structures systems including aircraft, missiles munitions is presented in this paper. technology currently being applied the structural health monitoring accelerometers, gyroscopes vibration devices with signal processing electronics provide real- time indicators incipient failure aircraft components a known history...
The authors propose a high efficacy alternating current plasma display panel utilizing vertically raised multilayer bus electrodes. cell structure was designed to provide an opposite discharge mode and low in relatively long gap. test panels having gaps of 330, 350, 370μm were fabricated basic properties the investigated terms current-voltage characteristics, luminance, luminous efficiency. cells with proposed show higher luminance lower simultaneously. improvement efficiency is found be...
A simplified mathematical model to predict the performance of a circulating fluidized bed boiler, which was previously developed along with pilot-scale extended accommodate configuration 300 MWe class boiler. The is combination zero-dimensional energy and mass balance heat exchanger blocks, across streams air combustion gas, water steam, solids interact. system describes boiler as blocks through solid–gas flow interacts water–steam transfer rates are determined by defining coefficients...
Package warpage significantly affects the yield and reliability of package assemblies such as POP board level surface mount. As size silicon die is fixed its thickness usually thinned down to minimum, only remaining variables control are substrate EMC. Therefore, co-optimization EMC critical improve behavior throughout assembly temperature profile for best reliability. Using simple bilayer structured specimens composed various substrates EMC's, we measure which dependent on their CTE,...
For Advanced Packaging (AP), it is essential to use Flip-chip Ball Grid Array(FCBGA), and Ajinomoto Build-up Film (ABF) employed as the build-up material for implementing fine trace patterns. In cases where size of substrate needs increase due multifunctionality, there a necessity thicken Center Core (CCL, Copper Clad Laminate) minimize risk warpage, which causes limitations in board design reduces electrical performance (SI/PI). this paper, we focus on FCBGA utilizing Prepreg, aiming...
Advanced prepreg (PPG) contains a low CTE glass fabric that is impregnated with resin filled fillers. A typical volume fraction of the in advanced PPG relatively small (approximately 20%), and still plays an important role behavior PPG. PPGs are laminated by thermal compression process. The residual stresses produced PPG, inherently mechanical interactions among fabric, filler during lamination as well cooling When subject to solder reflow process, magnitude stress changes because relaxation...
The vacuum die casting is a promising candidate of the stamping process for fabrication fuel cell bipolar plate due to its advantages, such as precision casting, mass production and short time. This study proposes fabricate plates in cell. Bipolar were fabricated under various injection conditions molten metal temperature velocity. Also, according velocity conditions, simulation results MAGMA soft compared experimental results. In case melt <TEX>$650^{\circ}C$</TEX>, misrun occurred. When...
Entire TDM-PON will get into a trouble even when only an ONU transmits optical signal constantly. This paper proposes scheme to find the failed ONU. CDMA coding is used for upstream transmission in situation.
This paper describes a fully integrated 8-channel front-end module (FEM) single chip IC fabricated with 45-nm RFSOI CMOS process technology for 5G mm-Wave application supporting n257/258/261 triple bands. Its silicon area is 4.29mm × 2.76mm which comprised of high efficiency Doherty topology power amplifier, low noise T/Rx switch, MIPI interface controller and so on. To address assembly limitation on the mm-wave antenna PCB, an ultra-thin Embedded Die Substrate (EDS) package adopted realizes...