A5050565374- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Photonic and Optical Devices
- Microwave Engineering and Waveguides
- Semiconductor materials and devices
- Semiconductor Lasers and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Quantum and electron transport phenomena
- Millimeter-Wave Propagation and Modeling
- Quantum Computing Algorithms and Architecture
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Power Amplifier Design
- Acoustic Wave Resonator Technologies
- Quantum chaos and dynamical systems
- Neuroscience and Neural Engineering
- Chaos control and synchronization
- VLSI and Analog Circuit Testing
- Quantum-Dot Cellular Automata
- Electrostatic Discharge in Electronics
- Advanced MEMS and NEMS Technologies
- CCD and CMOS Imaging Sensors
- Engineering Education and Technology
- Ferroelectric and Negative Capacitance Devices
University College Dublin
2017-2025
Tokyo Institute of Technology
2012-2019
Kwangwoon University
2014
Korea University
2014
Thammasat University
2008-2010
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, current output digital-to-analog converter (DAC), and fine resolution digital varactor. All circuits that make up the PLL are designed implemented using standard cells without any modification, automatically Place-and-routed (P&R) by design flow manual placement. Implemented in 65 nm CMOS process, this work occupies only 110 μm × 60 layout area, which...
This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker upconversion proper terminations. A 2nd-harmonic resonance is assisted by proposed embedded decoupling capacitor inside transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting techniques allow maintaining high quality factor of 10-GHz tank the 30-GHz generation. We...
This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and two-stream frequency-interleaved (FI) transceiver. The are both fabricated in standard 65-nm technology. For the proposed transceiver, TX-to-RX error vector magnitude (EVM) is less than -23.9 dB for 64-QAM wireless communication all four channels defined IEEE 802.11ad/WiGig. maximum distance full rate reach 0.13...
This paper presents a low-power low-noise 60 GHz frequency synthesizer using 20 subsampling phase-locked loop (SS-PLL) and tail-coupling quadrature injection-locked oscillator (QILO) which results in lower in-band phase noise out-of-band noise, respectively. To save battery life, dual-step-mixing divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique QILO helps boost negative transconductance (-g <sub...
This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy low power consumption is integrated with transceiver. With help of proposed calibration, this capable boosting data rate higher order modulation scheme wider channel-bonding bandwidth, which are demanded by 802.11ay. At same time, it maintains compatibility existing 802.11ad reports two-channel-bonding 24.64...
This paper presents a low-jitter, low-power and small-area injection-locked all-digital PLL (IL-ADPLL). It consists of dual-loop dual-VCO architecture in which one VCO (Replica) is placed TDC-less synthesizable ADFLL to provide continuous tracking voltage temperature variations. The other (main) shares the control with replica but outside loop lower its jitter accurately set frequency desired one. approach avoids timing problems conventional ILPLL since feedback loop. also achieves low power...
This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by analog-to-digital converter (ADC) instead of adopting traditional time-to-digital (TDC) which usually suffers from tradeoff in resolution and power consumption. It consists 18 bit class-C digitally controlled oscillator (DCO), 4 comparator, digital filter (DLF), frequency-locked (FLL). Implemented 65 nm CMOS technology, the proposed PLL reaches in-band phase noise -112 dBc/Hz RMS...
This paper proposes a sub-harmonic injection-locked frequency synthesizer with calibration scheme for millimeter-wave Time-division Duplexing (TDD) transceivers. The proposed is capable of supporting all 60 GHz channels (58.1-65 GHz) including channel-bonding defined by wireless standards short-range high-speed communications. In order to guarantee robust performance over process-voltage-temperature (PVT) variations the conventional synthesizer, automatically correct drift quadrature...
Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems. All-digital PLLs have been proposed to address design issues conventional analog PLLs. However, current all-digital require custom circuit design, and therefore cannot fully leverage advanced automated flows. While synthesizable reported, they suffer from high power consumption large area. This arises because each stage of the ring needs a number parallel tristate buffers/inverters order achieve...
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, internal switched-capacitor dc-dc converter "doubles" the supply voltage to all digital circuitry and particularly regulates time-to-digital (TDC) stabilize resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, temperature (PVT). The ADPLL supports two-point modulation...
This paper discloses a mixed-signal control unit of fully integrated semiconductor quantum processor SoC realized in 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width signals were for each qubit, enabling both programmable qubit operation per-qubit individual calibration compensates process variability. The lower deco-herence time charge-qubits as compared to their spin-qubit counterparts was mitigated by using high frequency operation. is...
Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1], [2] due to their ability achieve ultra-low jitter (<; 100fs). However, as indicated in Fig. 17.6.1 (top-left), sub-sampling PLLs (SS-PLL) typically suffer from high-power consumption, especially mmW VCO buffers, which isolate the its sampler reducing reference spurs, high-speed dividers [2]-[4]. Also, analog loop filter usually occupies large area....
Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using pure digital design flow, have been proposed to reduce the cost allow easier integration. To achieve high-frequency resolution, required operate fractional-N mode, addition integer-N mode. There several architectures available [5-6] for realizing operation....
The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, IEEE802.11ay standard is one of most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at are considered to be used standard. However, more severe requirements LO feedthrough (LOFT) image-rejection ratio (IMRR) have satisfied, so much higher accuracy...
It is predicted that the required wireless communication capacity will become 1000 times higher every 10 years. Many standards are under discussion to satisfy unprecedented requirement. For example, IEEE802.11ay standard targeting over 100Gb/s data-rate by using 60GHz band. Unfortunately, channel bandwidth of 2.16GHz for band not wide enough realize such a high data-rate, so channel-bonding capability strongly demanded extend as well 64-QAM support, achieving 42.24Gb/s. To 4-channel bonding...
A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical supporting ultra-low PN frequency generation for the advanced communications and other emerging high-speed applications. Unfortunately, current literature either full conflicting theories ambiguities or too complex mathematics, hiding physical insights. In this brief, we comprehensively review evolution upconversion clarify their controversial confusing parts. Two classes such mechanisms voltage-biased...
This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves 265-μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling without disturbing state of reduce number building blocks works at oscillator frequency, leading significant power reduction. With reduced high-frequency circuits, scaling reference frequency is fully used consumption DPLL. Together with an out-of-dead-zone detector and...
This brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators reduced conduction angle (i.e., class-C), which has been presented literature but never properly explained. The phase a voltage-biased oscillator capable operating class-B class-C is compared verified using commercial simulation model TSMC 28-nm CMOS. We illustrate how narrowing can suppress 1/f up-conversion by decreasing exposure asymmetric rising falling edges...
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog (C-DAC) array is used to regulate the starting supply voltage of constant discharging slope fed fixed-threshold comparator. The DTC operation mechanism analyzed and design tradeoffs are investigated. proposed consumes merely 31 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are local well areas separated by tunnel barriers controlled gate terminals overlapping with thin 5-nm undoped silicon film. Interface of the quantum structure classical electronic circuitry is provided transistors that feature doped wells on classic side. A small 0.7 ×0.4 μm <sup...
This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and doublers to achieve low in-band out-of-band phase-noise for 5G mobile communications. The push-push amplifier 28GHz balun help achieving differential signals with phase noise while consuming power. A charge pump gated offset as well doubler reducing noise-folding effect resulting sampling loop filter helps spurs. proposed has been implemented in 65nm CMOS technology an of -78dBc/Hz -126dBc/Hz,...
This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. allows the proposed to achieve relatively lower in-band phase noise through use of sub-sampling operation, as well good out-of-band injection. The has been implemented in standard 65-nm CMOS technology. It can support all channels and achieves −115dBc/Hz at 10MHz offset. operation helps reducing an integrated jitter from 12ps 2.1ps. consumes 20.2mW 14mW 20GHz phase-locked...