A5039873132- Advancements in PLL and VCO Technologies
- Radiation Effects in Electronics
- Particle Detector Development and Performance
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Radiation Detection and Scintillator Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Interconnection Networks and Systems
- CCD and CMOS Imaging Sensors
- Analog and Mixed-Signal Circuit Design
- Semiconductor Quantum Structures and Devices
- Electromagnetic Compatibility and Noise Suppression
- Advanced Optical Sensing Technologies
- Particle Accelerators and Free-Electron Lasers
- 3D IC and TSV technologies
- Advanced Data Storage Technologies
- Silicon Carbide Semiconductor Technologies
- Electrostatic Discharge in Electronics
- Parallel Computing and Optimization Techniques
- Distributed and Parallel Computing Systems
European Organization for Nuclear Research
2015-2024
Southern Methodist University
2023
KU Leuven
2016-2020
Brandenburg University of Technology Cottbus-Senftenberg
2020
The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data in the physics experiments of future upgrade LHC accelerator, SLHC. Due to high beam luminosity planned SLHC, will require rate links electronic components capable sustaining radiation doses. GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between counting room experiments. paper describes detail GBT-SERDES presents an overview various that...
The future upgrades of the LHC experiments will increase beam luminosity leading to a corresponding growth amounts data be treated by acquisition systems. To address these needs, GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed provide simultaneous transfer readout data, timing and trigger signals as well slow control monitoring data. GBT-SCA ASIC, part chip-set, has purpose distribute on-detector front-end electronics perform operations detector environmental...
In the framework of GigaBit Transceiver project (GBT), a prototype, GBT-SerDes ASIC, was developed, fabricated and tested.To sustain high radiation doses while operating at 4.8Gb/s, ASIC in commercial 130 nm CMOS technology employing tolerant techniques circuits.The transceiver serializes-deserializes data, Reed-Solomon encodes decodes data scrambles descrambles for transmission over optical fibre links.This paper describes architecture, presents test results.
In this work, a comparison has been made between low noise ring-oscillator and an LC-oscillator Phase Locked Loop (PLL). An ASIC developed to conduct irradiation experiments targeting high-energy physics applications. Two different samples were irradiated up total ionizing dose (TID) in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> of 200 Mrad 600 with 100°C thermal annealing step. Single-Event Upset (SEU) tests performed heavy...
Abstract With over 6 million channels, the High Granularity Calorimeter for CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide critical stage of on-detector compression and selection trigger path (ECON-T) acquisition (ECON-D) HGCAL. ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad require low power consumption: < 2.5 mW/sensor-channel per chip. We report on first functionality tests ECON-D-P1 full-functionality prototype. present...
The future upgrade of the LHC accelerator, SLHC, will increase beam luminosity by a factor ten leading to corresponding growth amounts data be treated transmission and acquisition systems. development GBT chipset addresses this issue providing means bandwidth available transmit from counting room. GigaBit Transceiver (GBT) architecture provide support simultaneously three types information required run an experiment in hostile radiation environment over multipurpose link. This paper...
This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event upsets (SEUs). The is designed high-energy particle physics experiments low-jitter clock generation and recovery. An optimal tuning strategy of the VCO presented that minimizes cross section SEU sensitivity oscillator. processed in 65-nm technology has been irradiated heavy ions linear energy transfer between 10 to...
Abstract The performance of ASICs for high-bandwidth communications is heavily influenced by the interconnection with hosting module and paired devices, including bonding scheme PCB layout. recent validation campaign 25.6 Gbps DART28 transmitter has highlighted that a coordinated simulation design power delivery network required to achieve satisfactory performance. In this context, results obtained from variants test-bench carrier boards are compared, examining how optimisation layout...
Abstract With over 6 million channels, the High Granularity Calorimeter (HGCAL) for CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector reduction 40 MHz trigger path (ECON-T) and 750 kHz acquisition (ECON-D) of HGCAL. ASICs, fabricated in 65 nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel). This presentation is first comprehensive description designs, functionality radiation tests ECON-T ASIC, results from full...
This paper presents the development of GBTX radiation hard ASIC test bench. Developed for LHC accelerator upgrade programs, implements a bidirectional 4.8 Gb/s link between on-detector custom electronics and off-detector systems. The bench was used functional testing to evaluate its performance in environment, by conducting Total Ionizing Dose Single-Event Upsets tests campaigns.
Abstract Pioneering physics experiments require increasingly faster data transfers and high-throughput electronics, which drives the research towards a new class of serialisers optical links. In this framework, DART28, 100 Gbps radiation tolerant serialiser driver, has been designed in 28 nm CMOS technology, submitted April delivered August 2023. The development coupled with an FPGA based emulation, provided early assessment its behaviour, scalable system-level demonstrator effective...
Abstract The paper presents the D ual U se riv e r (DUDE) for high speed links, a circuit designed Demonstrator ASIC Radiation-Tolerant Transmitter in 28 nm CMOS (DART28) developed under EP-R&D programme on technologies future energy physics experiments. driver operates at 25.6 Gbps and it allows driving both 100 Ω transmission lines optical Ring Modulators (RMs) integrated photonics (PIC). includes configurable pre-emphasis. device will allow to demonstrate feasibility of wavelength...
In the future LHC experiments, some data acquisition and trigger links will be based on Gbit/s optical fiber networks. this paper, a configurable radiation tolerant serializer (GOL) is presented that addresses high-energy physics experiments requirements. The device can operate in four different modes are combination of two transmission protocols rates (0.8 1.6 Gbit/s). ASIC may used as transmitter that, otherwise, use only commercial components. encoding schemes supported CIMT (G-Link)...
The GigaBit Transceiver (GBT) is a high-speed optical transmission system currently under development for HEP applications. This will implement bi-directional links to be used in the radiation environment of Super LHC. Transimpedance Amplifier (GBTIA) front-end receiver GBT chip set. paper presents GBTIA, 5 Gbit/s, fully differential, and highly sensitive designed implemented commercial 0.13 µm CMOS process. When connected PIN-diode, GBTIA displays sensitivity better than 19 dBm BER 10 12...
This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The has been implemented 65 nm CMOS technology. A noise LC-tank oscillator is included with tuning range from 2.2 GHz to 3.2 GHz. includes new phase detector divider Triple Modular Redundancy (TMR) suppress Effects ionizing radiation environments. highly reconfigurable bandwidth 0.7 MHz 2 provides optimal reference filtering. designed...
The e-link, an electrical interface suitable for transmission of data over PCBs or cables, within a distance few meters, at rates up to 320 Mbit/s, is presented. elink targeted the connection between GigaBit Transceiver (GBTX) chip and Front-End (FE) integrated circuits. A commercial component complying with Scalable LowVoltage Signaling (SLVS) standard was tested demonstrated performance level compatible our application. Test results are SLVS transmitter/receiver IP block designed in 130 nm...
We present the design, architecture and experimental results of low jitter Clock Data Recovery (CDR) Phase Locked Loop (PLL) circuit in Low-Power Gigabit Transceiver (lpGBT) ASIC. This includes a noise radiation-tolerant integrated LC-oscillator with nominal frequency 5.12 GHz to support 10.24 Gbps uplink 2.56 downlink CDR. CDR employs novel loop high-speed feed forward stabilization technique. A test was fabricated 65 nm CMOS technology has been tested experimentally for correct operation...
Abstract The Low Power GigaBit Transceiver (lpGBT) is a radiation-tolerant Application-Specific Integrated Circuit (ASIC) designed to implement versatile high-speed bi-directional serial links in the experiments and environment of Large Hadron Collider. With 336 programmable registers 11 configuration pins, this ASIC highly configurable. current version chip, lpGBTv1, now under test. project will then produce chips equip phase-2 experiment upgrades starting 2025. More than 180000 components...
Abstract Ongoing developments in the field of radiation-tolerant high-speed transmitters (HSTs) aim at increasing data rates above 25 Gb/s while total ionizing dose (TID) tolerance 1 Grad. The use half-rate architectures imposes tight constraints on clock signal quality, particular its duty-cycle. Radiation degradation transistors path causes duty cycle distortion (DCD), affecting output quality HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is...
This paper presents a 25.6 Gbit s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> high-speed transmitter (HST) manufactured using 28nm CMOS technology. The HST macro-block includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and driver capable of driving the differential 100Ω line as well silicon photonics (SiPh) ring modulator (RM). design adopts various radiation...
The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC which part of the Transceiver (GBT) chipset. It aimed to drive both edge emitting and VCSEL laser diodes at data rate in excess 5 Gb/s. GBLD can provide modulation current up 24 mA bias 43 mA. Pre- de-emphasis functions are implemented compensate for high external capacitive loads asymmetric response. chip designed 130 nm CMOS technology powered by single 2.5 V supply.
Photodiodes are important components in optical data links, and their performance degradation under irradiation has to be understood order guarantee the long-term functionality of links radiation environments high-energy physics experiments. Indium gallium arsenide (InGaAs) on indium phosphide (InP) photodiodes attractive candidates for these applications, thanks relatively modest radiation-induced responsivity loss when operated at 850 nm. In this paper, we present results that confirm...