A5102776495- Radiation Effects in Electronics
- Advancements in PLL and VCO Technologies
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Radio Frequency Integrated Circuit Design
- Particle Detector Development and Performance
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Therapy and Dosimetry
- Adversarial Robustness in Machine Learning
- Photonic and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Radiation Detection and Scintillator Technologies
- Physical Unclonable Functions (PUFs) and Hardware Security
- Engineering and Test Systems
- Interconnection Networks and Systems
- Semiconductor Lasers and Optical Devices
- Spacecraft Design and Technology
- Analog and Mixed-Signal Circuit Design
- Advanced Photonic Communication Systems
- Embedded Systems Design Techniques
- Advanced Memory and Neural Computing
- Silicon and Solar Cell Technologies
- CCD and CMOS Imaging Sensors
KU Leuven
2019-2025
Brandenburg University of Technology Cottbus-Senftenberg
2020
European Organization for Nuclear Research
2020
Abstract With over 6 million channels, the High Granularity Calorimeter for CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide critical stage of on-detector compression and selection trigger path (ECON-T) acquisition (ECON-D) HGCAL. ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad require low power consumption: < 2.5 mW/sensor-channel per chip. We report on first functionality tests ECON-D-P1 full-functionality prototype. present...
Deep neural networks (DNNs) are increasingly used in safety-critical applications. Reliable fault analysis and mitigation essential to ensure their functionality harsh environments that contain high radiation levels. This study analyses the impact of multiple single-bit single-event upsets DNNs by performing injection at level a DNN model. Additionally, aware training (FAT) methodology is proposed improves DNNs' robustness faults without any modification hardware. Experimental results show...
Abstract Deep neural networks (DNNs) are increasingly used in safety-critical applications. Reliable fault analysis and mitigation essential to ensure their functionality harsh environments that contain high radiation levels. This study analyses the impact of multiple single-bit single-event upsets DNNs by performing injection at level a DNN model. Additionally, fault-aware training (FAT) methodology is proposed improves DNNs' robustness faults without any modification hardware. Experimental...
Abstract With over 6 million channels, the High Granularity Calorimeter (HGCAL) for CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector reduction 40 MHz trigger path (ECON-T) and 750 kHz acquisition (ECON-D) of HGCAL. ASICs, fabricated in 65 nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel). This presentation is first comprehensive description designs, functionality radiation tests ECON-T ASIC, results from full...
This article presents a static random access memory (SRAM)-based flexible radiation monitor. The monitor was fabricated in 65-nm CMOS technology and it is designed as an application-specific integrated circuit, which comprises 768k bits SRAM cell matrix with individual power supply digital control core serial peripheral interface (SPI). By adjusting the voltage of matrix, sensitivity made flexible. Also, cells different threshold voltages were implemented to get further extension on tunable...
Abstract Ongoing developments in the field of radiation-tolerant high-speed transmitters (HSTs) aim at increasing data rates above 25 Gb/s while total ionizing dose (TID) tolerance 1 Grad. The use half-rate architectures imposes tight constraints on clock signal quality, particular its duty-cycle. Radiation degradation transistors path causes duty cycle distortion (DCD), affecting output quality HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is...
This paper presents a 25.6 Gbit s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> high-speed transmitter (HST) manufactured using 28nm CMOS technology. The HST macro-block includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and driver capable of driving the differential 100Ω line as well silicon photonics (SiPh) ring modulator (RM). design adopts various radiation...
We present the design, architecture and experimental results of low jitter Clock Data Recovery (CDR) Phase Locked Loop (PLL) circuit in Low-Power Gigabit Transceiver (lpGBT) ASIC. This includes a noise radiation-tolerant integrated LC-oscillator with nominal frequency 5.12 GHz to support 10.24 Gbps uplink 2.56 downlink CDR. CDR employs novel loop high-speed feed forward stabilization technique. A test was fabricated 65 nm CMOS technology has been tested experimentally for correct operation...
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) includes high-speed feed-forward path, which stabilizes the by compensating an additional pole introduced in VCO order to harden it against ionizing particles. has data rate of 2.56 Gb/s uses In-Phase/Quadrature (IQ) clocks combination with frequency detector (FD) increase...
This article describes a previously unreported single-event radiation effect in spiral inductors manufactured commercial CMOS technology when subjected to ionizing radiation. Inductors play major role as the component determining frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank oscillators, which is why any these passive components can have detrimental...
This article presents a radiation-tolerant digitally controlled complementary metal–oxide–semiconductor (CMOS) ring oscillator design suitable for all-digital phase-locked loop (ADPLL) implementations. To address the challenges presented by harsh radiation environments, wide tuning range architecture is with superior single-event effect (SEE) tolerance. The proposed circuit characterized experimentally in 65-nm technology and shown to achieve significant reduction SEE...
Time-to-digital converters (TDCs) with superior performance are in high demand application domains like light detection and ranging (LIDAR), nuclear physics, time interval counters. One of the interesting architectures for field-programmable gate array (FPGA)-based TDCs is tapped delay line (TDL) approach carry chains as elements. However, resolution TDL-TDCs limited, linearity weakened by ultra-wide bins that correspond to FPGA’s long routing wires crossing into another clock area. This...
This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The uses distributed placement strategy compared to commonly used bulk 3-bank constraining method. TMR netlist information is optimally constrain the of both sequential cells and combinational cells. approach significantly reduces routing complexity, net lengths dynamic power consumption with more than 60% 20% respectively....
This article presents a radiation tolerant charge-pump phase-locked loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose environments. We investigate the use of source switching architectures to minimize any voltage- or dose-dependent charge injection and address limitations enclosed layout transistors (ELTs) conventional drain switched charge-pump. The circuit has been processed 65-nm complementary metal–oxide–semiconductor (CMOS)...
Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear up to space applications. The long-term reliability of these is essential safe operation. However, the effects ICs commonly investigated using fresh circuits, leaving coupled effect and aging degradation unknown. This article investigates impact negative bias temperature instability (NBTI) mechanism on heavy-ion single event upset (SEU)...
This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with resolution of 15.6 ps, fabricated in 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on multipath pseudo differential ring oscillator reduced phase delay, without the need for calibration or interpolation. placed inside Phase Locked Loop (PLL) to compensate Process, Voltage and Temperature (PVT) variations- variations due ionizing radiation. Measurements evaluate...
This paper presents a general theory of time-dependent single-event effects in CMOS LC-oscillators. The analysis employs the oscillator's impulse-sensitive function (ISF) to calculate effect transient current due an ionizing particle. A discussion is made on dependence maximum junction collection and modulation this with voltage-controlled oscillator (VCO) signal waveform, supported by TCAD simulations. An experimental study using two-photon absorption (TPA) laser setup performed obtain...
Performance degradation of standard time-to-digital converters (TDCs) is inevitable due to the effects ionizing radiation. In this article, tradeoffs different mitigation techniques for TDC architectures are presented. As effect radiation challenging such high-performance circuits in state-of-the-art technologies, that can compensate have become a necessity TDCs operate these harsh environments. By looking into functionality focusing on improving tolerance, main weak and strong points...
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity Single-Event Effects (SEEs) up 62.5 MeV cm2 mg−1 as well tolerance Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding use of a highly SEE...
Experimental mono-energetic proton single-event upset (SEU) cross-sections of a 65 nm low core-voltage static random access memory (SRAM) were found to be exceptionally high not only at energies (< 3 MeV), but also > MeV and extending up tens MeV. The SEU cross-section from 20 protons exceed the 200 by almost factor 3. Similarly, neutron 14 are about lower than cross-section. Thanks Monte-Carlo (MC) simulations it was determined that this strong enhancement is due direct ionization process...
Abstract True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed low power consumption, compared to static FFs. Due the relatively leakage currents modern CMOS processes, use of protection techniques storage nodes must be considered, especially at radiation doses. In this paper, limitations originating from Total Ionization Dose...
In this paper, a time-variant analysis is made on Single-Event Transients (SETs) in integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator used to analyze impact relative moment when particle hits circuit. based simulations and verified experimentally with Two-Photon Absorption (TPA) laser setup. experiments are done using 65 nm test chip.
In this paper, for the first time, phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to three stages conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved increasing stages. The primary distinction between these two designs (SDRO three-stage CROs) inherent skew offset PMOS/NMOS gates caused by unique connection. This fundamental cause delay cell suppression; have loosely coupled...