Homodyne-based digital modulators are widely used in navigation satellite systems, such as the Navigation with Indian Constellation (NavIC). In these mixer plays a crucial role by up-converting zero-IF complex modulated signals to desired carrier frequency. However, insufficient port-to-port isolation can cause leakage of local oscillator (LO) into output, resulting unwanted in-band within transmitted spectrum. When leaked amplified transmit filters and onboard high-power amplifiers, they...

A well-calibrated numerical-simulation-based study reveals that an elongated extension region can be a notable approach for the self-heating mitigation of nanosheet FETs. It is observed longer length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{L}_{\text{EXT}}$</tex-math> </inline-formula> notation="LaTeX">$=$</tex-math> 8 nm) reduces ON current; however, it holds smaller penalty in...

This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The architecture has cells' inputs separated optimized skew offset. Skew-offset optimization is attained integrating pre-charge/discharge auxiliary feed-forward loop into separately driven reduces transition time when <italic xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time estimating aging-aware path-level performance and its impact logical effort of a CMOS inverter digital closure in pre-stress post-stress conditions. Degradation threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ th}})$ </tex-math></inline-formula> PMOS...

This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using tool flow methodology based Python and Bash scripting. The involves creating an effective current source model (ECSM) .libs file with custom flow, which incorporates variation-aware models of standard cells to minimize recharacterization efforts. resulting is integrated into industry-standard STA environment assess the impact device layout level variability...

This paper introduces a new set of objective functions and presents design flow for near-perfect reconstruction (NPR) analysis synthesis filter-bank based transmultiplexer. The effects constraints in terms filter order coefficients quantization are analysed their effect on overall response cross-channel interference; this leading to an optimum choice the prototype with iterative process. Using method, 16-channel transmultiplexer was designed onboard transparent processor suit requirement...

Due to the highly variation-prone nature of near-threshold voltage (NTV) circuits, it is critical have design and performance models that consider process, voltage, temperature (PVT) variations. However, in NTV regime, existing timing are based on arbitrarily chosen VDD-dependent threshold points for effective current calculation results unreliability. In this article, an delay model inverter operating regime presented using supply-independent points. The developed considering input-output...

This brief presents a general approach for generating high-frequency multiphase signals (even/odd), low phase noise, power, and reduced supply sensitivity ring oscillators (ROs). For the same, multi-loop skew based single-ended (MSSROs) are designed systematic analysis is performed. The topology on unique feedback/feed-forward mechanism realizing fast loop in long chain RO wherein PMOS/NMOS of stages separately driven. connection MSSROs results offset (negative/positive/zero) which generated...

This paper describes an efficient design of digital transparent processor payload subsystem, developed at Space Applications Centre (ISRO) for a multi-beam, high throughput communication satellite. The processor, also called mesh onboard multi-beam satellite performs the functions slicing uplink bandwidth into fine granules, switching it as per user requirements and combining bandwidth-granules downlink transmission. It effectively serves exchange-in-the-sky providing inter-beam intra-beam...

A wide tuning range, low VCO gain and a PVT variations are the requirements for Ring Oscillators at near threshold voltages (NTV). Current starved ring oscillators (CSRO) have voltage headroom issues in NTV regime. MOS varactor based single ended oscillator (SERO) is best suited its full swing characteristics, range power consumption. However, high nonlinearity limitations. This paper proposes bulk driven SERO (BD-MOS) that gives linear from 0 to VDD Post layout simulations been performed on...

In this paper, for the first time, phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to three stages conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved increasing stages. The primary distinction between these two designs (SDRO three-stage CROs) inherent skew offset PMOS/NMOS gates caused by unique connection. This fundamental cause delay cell suppression; have loosely coupled...

In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models conventional, bulk-driven (BD), dynamic-threshold (DT) MV-VCROs considering nonlinearity NTV presented using effective drive current ( I <sub...

In stress enabled technologies the drive strength of multi-fingered (MF) transistors varies with number fingers (NF) because Layout Dependent Effect (LDE). This is an important issue MF are widely used in integrated circuits. this paper, we investigate performance variability issues basic analog building blocks, such as current mirrors, common source amplifiers, and single ended differential designed using transistors. We observe that, due to layout dependent channel mechanical stress,...

Due to small output swings and series stack transistors, Differential Ring Oscillators (DRO) current starved ROs are not well suited for Near Threshold Voltage (NTV) regime. MOS varactor based Single Ended (SERO) is in NTV regime as it gives full swing characteristics, wide tuning range has very low power consumption. This paper proposes different architectures using Varactor SERO (VBRO) that high oscillation frequency, range, area consumption without degrading the phase noise compared...

FPGA implementation of computation intensive signal processing algorithms for satellite onboard applications require careful considerations resource utilization and power consumption. In this paper, we describe several strategies used efficient the synthesis filter banks digital spectrum modules on FPGA. Xilinx Virtex-5 series was chosen design verification model. Even though FPGAs have sufficiently large logic resources most common applications, fairly requires innovative code, described in...

Laboratory testing of digital beamforming processor is required to test and optimize the beamformer algorithm, code hardware before integrating with antenna in an anechoic chamber.Development a stimulus generator, for carrying out such exercise, itself can be quite involved task employing large phased array antenna.This paper proposes innovative design generator receive system.A reconfigurable prototype, Xilinx Virtex-5 FPGA based architecture, developed generate IF 8-elements beamformer.It...

A DC-DC boost converter is widely used for power management applications. However, the right-half-plane zero effect still remains a bottleneck fast transient recovery. This paper intended to propose an embedded reconfigurable solution with ultra-fast recovery through near-lossless augmentation. augmentation branch requires extra synchronous phase in parallel, comprising small inductor and half-bridge switch cell. activated only during large-signal The original topology restored steady state...

Nowadays, use of higher carrier frequencies for data transmission in wireless communication has created a demand Direct RF Sampling ADCs with sampling clocks and larger analog bandwidths. With the increase rate there is need clock speed capable ASIC/FPGAs faster acquisition efficient signal processing. Though ASICs are best method to achieve required speeds their NRE Costs, Fabrication cost Time market put them second position when compared FPGAs which highly reconfigurable, features less...

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage design is presented for near-threshold voltage (NTV) regime where non-linearities dominates. For first time, model accounts due to over/undershoot region which critical in NTV regime. Further, uses effective drive current, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">...