Yield improvement, yield ramp, and defect screening have been major areas of concern for the semiconductor industry as technology nodes advanced. Much effort has focused on capturing defects missed by traditional stuck-at transition delay fault model based testing. A majority these un-modeled stems from features inside a standard cell or between two adjacent cells. Traditionally, critical area used manufacturability guideline to determine opens shorts that should be targeted test. This paper...

Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show in 0.13 /spl mu/m such noise local embedded combinational exceed the threshold voltage. We impact on different kinds circuits. The magnitude this increase due process variations. present an algorithm for generating vectors validation manufacturing test detect logic-value errors caused by inductance induced oscillation. To facilitate vector...

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of ensures that state-of-the-art process can be used estimating delays. However, analysis, by itself, inaccurate as it does not take into consideration conditions are necessary detecting faults. In the proposed method, these captured what called input assignments, which tools able use. By providing with assignments selected path, estimate more...

In this paper, a new algorithm is proposed for fast kernel density estimation (FKDE), based on principal direction divisive partitioning (PDDP) of the data space. A framework also developed to apply FKDE algorithms (both and existing), within nonparametric noncausal Markov random field (NNMRF) texture synthesis algorithm. The goal use finite support property kernels density. It has been shown that hyperplane boundaries space component vectors are two requirements efficient FKDE. compared...

Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show in 0.13 /spl mu/m such noise local embedded combinational exceed the threshold voltage. We impact on different kinds circuits. The magnitude this increase due process variations. present an algorithm for generating vectors validation manufacturing test detect logic-value errors caused by inductance induced oscillation. To facilitate vector...

Nowadays, Architecture Description Languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of Application Specific Instruction-Set Processors (ASIPs). Verification, in various stages such ASIP development, is a major bottleneck hindering widespread acceptance ADL-based processor approach. Traditional verification processors only applied at Register Transfer Level (RTL) or below. In context design, this approach often inconvenient...

Capacitive crosstalk can slowdown transitions which propagate to outputs and cause erroneous operation. Test generation methods such as XGEN XGEN-E were proposed generate tests for failures. However, a drawback of these test is that large proportion faults are aborted. In this paper, we systematically derive multi-valued algebra. We first show composite value system must be derived considering all operations performed by the algorithm will use system. particular, identify our it imperative...

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among faults obtained DFM guidelines, there are undetectable faults, and these cluster in certain areas circuit. Because may not perfectly represent defect behaviors, detectable even though that model them undetectable. Clusters...

Recent advances in process technology have resulted novel defect mechanisms making the test generation very challenging. In addition to complete opens and shorts that can be represented via extreme resistance magnitudes, partial resistive are also of concern deeply scaled CMOS technologies. For open defects with intermediate magnitude values, it has been shown multi-pattern tests necessary for exposure. We extend this approach short values obtain a suite standard cell instances cover as well...

Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge the IC test industry. Traditional methods using fault models such as stuck-at and transition faults with primitive gate-level abstraction of design netlists have shown to be inadequate detecting open-circuit short-circuit defects within instances standard cells used in those netlists. Recent advances Cell-Aware Test (CAT) single pattern two tests demonstrated increased industrial designs. However,...

Ensuring a tight correlation between pre-silicon static timing analysis (STA) and post-silicon is essential to robust design flow. Researchers from Intel describe novel methodology validate path level STA on silicon using standard scan architecture delay tests that are generated by commercial EDA tools.

Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown need for multi-pattern tests where intermediate resistance values concerned, as opposed extreme considered prevalent techniques. In this research, we show that there exist ranges short escape traditional while...

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture features that difficult manufacture correctly. Avoiding such prevents the occurrence of potential systematic defects. Layout result in DFM guideline violations may not be avoided completely due constraints chip area, performance, and power consumption. A framework for translating into defects, faults, was described earlier. In a cell-based design, translated faults internal or external...

The impact of di/dt noise and static IR drop on at-speed scan testing has been reported in literature. Delays paths can be impacted during delay by ways that change the ordering paths. This, turn, affects ability such tests to catch certain defects impairs its use for speed binning. It is important, therefore, address tests. This paper proposes an instrumentation methodology a design based launch-off-capture control time interval between shift capture cycles. mechanism improves...

The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower resistance values and fast signal transition times. accurate modeling of behavior is thus essential high speed VLSI designs. Recently X architecture has been introduced reduce overall IC length by using diagonal wirings pervasively, resulting in smaller die sizes higher performance. Although the capacitance wires their are well understood, characterization studies wire remain...

We describe a novel methodology to validate path level static timing analysis (STA) on silicon by leveraging standard scan architecture and using hazard-free robust delay tests. have successfully validated sizable set of paths across multiple advanced process nodes. Learnings from these STA correlation exercises representative ASIC blocks in test chips resulted silicon-proven signoff with optimum guard-bands. The health feedback has proved valuable for the development team especially during...

A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in faulty chip. To reduce number candidates produced, diagnostic tests often needed. The use increases storage requirements test set. Earlier works reduced input fault detection by using each stored apply several different tests. When applied tests, were selected performing simulation basic model. In this paper, we approach target large sets candidate produced tool. for selection...

Process variations have an enormous impact on the amount of crosstalk in circuit. Aggravation may lead to erroneous behavior circuit resulting reduced product yield. Products failed meet targeted frequencies because problems. Therefore, a should be designed such that there is safety margin from operation. At same time, design not so conservative chip area and performance fall behind operational objectives. Whereas combination process parameters give rise worst-case noise context dependent,...

Summary form only given. In the industry today, testing packaged chips achieves outgoing DPPM (defective parts per million) requirements. Usually, functional and structural test patterns are used at wafer sort, followed by functional/structural with parts, then system level testing, each subsequent stage significantly more expensive than previous one. By large, have not been for performance binning reliability screening. Also, tested in burn-in chambers on load boards, using either same sort...