We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, we call Network-on-Chip (NOC), includes both the architecture and design methodology. NOC is m/spl times/n mesh switches resources are placed on slots formed by switches. assume direct layout 2-D providing physical- architectural-level integration. Each switch connected one resource four neighboring switches, each switch. A can be core, memory,...

In today's emerging Network-on-Chips, there is a need for different traffic classes with Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing Best-Effort (BE) packet delivery. The guaranteed bandwidth accessed via Virtual Circuits (VC). VCs are using combination two concepts that call Looped Containers' Temporally Disjoint Networks'. Containers used guarantee access...

We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order aid the designer selection process of what parts protocols, and their respective facilities, include, layered approach is taken. A nomenclature for describing individual layers' interfaces service definitions layers suggested used. The concept includes support best effort traffic packet delivery as well guaranteed bandwidth traffic, using virtual circuits. Furthermore an...

In today's emerging network-on-chips, there is a need for different traffic classes with quality-of-service guarantees. Within our NoC architecture nostrum, we have implemented service of guaranteed bandwidth (GB), and latency, in addition to the already existing best-effort (BE) packet delivery. The accessed via virtual circuits (VC). VCs are using combination two concepts that call 'Looped Containers' 'Temporally Disjoint Networks'. looped containers used guarantee access...

Self-awareness facilitates a proper assessment of cost-constrained cyber-physical systems, allocating limited resources where they are most needed. Together, situation awareness and attention key enablers for self-awareness in efficient distributed sensing computing networks.

Run-time partial reconfiguration (PR) speed is significant in applications especially when fast IP core switching required. In this paper, we propose to use direct memory access (DMA), master (MST) burst, and a dedicated block RAM (BRAM) cache respectively reduce the time. Based on Xilinx PR technology Internal Configuration Access Port (ICAP) primitive FPGA fabric, discuss multiple design architectures thoroughly investigate their performance with measurements for different bitstream sizes....

We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed takes as input application communication graph, topology mapping vector, and routing matrix, estimates average packet latency router blocking time. It works arbitrary network with deterministic under traffic patterns. This can estimate per-flow accurately quickly, thus enabling fast design space exploration of various parameters NoC designs. Experimental...

Due to the high integration density and roadblock of voltage scaling, modern multicore processors experience higher power densities than previous technology scaling nodes. When unattended, this issue might lead temperature hot spots, that in turn may cause nonuniform aging, accelerate chip failure, impair reliability, reduce performance system. This paper presents an overview several research efforts propose use machine learning (ML) techniques for thermal management on single-core...

The scope of the formal system design (ForSyDe) methodology is high-level modeling and refinement systems-on-a-chip embedded systems. Starting with a specification model, that captures functionality at high abstraction level, it provides design-transformation methods for transparent process model into an implementation optimized synthesis. main contribution this paper ForSyDe technique treatment transformational refinement. We introduce constructors, cleanly separate computation part from...

In networks on chip (NoC) very low cost and high performance switches are of critical importance. For a regular two-dimensional NoC, we propose simple, memoryless switch. the case congestion, packets emitted in non-ideal direction, also called deflective routing. To increase maximum tolerable load network, proximity congestion awareness (PCA) technique, where use information neighbouring switches, stress values, for their own switching decisions, thus avoiding congested areas. We present...

Continuing decrease in the feature size of integrated circuits leads to increases susceptibility transient and permanent faults. This paper proposes a fault-tolerant solution for bufferless network-on-chip, including an on-line fault-diagnosis mechanism detect both faults, hybrid automatic repeat request, forward error correction link-level control scheme handle faults reinforcement-learning-based deflection routing (FTDR) algorithm tolerate without deadlock livelock. A...

Embedded systems must address a multitude of potentially conflicting design constraints such as resiliency, energy, heat, cost, performance, security, etc., all in the face highly dynamic operational behaviors and environmental conditions. By incorporating elements intelligence, hope is that resulting “smart” embedded will function correctly within desired spite changes applications environment, well underlying software/hardware platforms. Since terms related to “smartness” (e.g.,...

In healthcare, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs exist as 24 hours prior having serious impact on the person. As hospitalization times have to be minimized, in-home or remote warning systems can fill gap by allowing care while potentially problematic conditions and their under surveillance control. This work presents diagnostic system that provides holistic perspective conditions. We discuss how concept self-awareness...

The reliability of a Network-on-Chip will be significantly influenced by the switch-to-switch connections. Faults on these buses may cause disturbances multiple adjacent wires, so that errors wires can no longer considered as statistically independent from one another, it is expected due to deep submicron effects. A new fault model notation for proposed which represent multiple-wire, multiple-cycle faults. An estimation method based this presented accurately predict error probabilities. This...

We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on reinforcement learning for NoC. The reconfigures the table through kind of learning---Q-learning using 2-hop fault information. It is topology-agnostic and insensitive to shape region. In order reduce size, we also hierarchical Q-learning (FTDR-H) with area reduction up 27% switch in an 8 x mesh compared original FTDR. Experimental results show that presence faults, FTDR FTDR-H are better than other...

In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns share buffers and link bandwidth using dedicated time slots. paper, we first give formulation multinode configuration problem for arbitrary NoC topologies. A allows multiple source destination nodes on it. Then address problems path...

This paper presents FPGA-based ECG arrhythmia detection using an Artificial Neural Network (ANN). The objective is to implement a neural network based machine learning algorithm on FPGA detect anomalies in signals, with better performance and accuracy, compared statistical methods. An implementation Principal Component Analysis (PCA) for feature reduction multi-layer perceptron (MLP) classification, proved superior other algorithms. For FPGA, the effects of several parameters simplification...

We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events, such as values or sequences. While in most cases these circuits are able to hide attack, exhaustive functional simulation and testing will reveal due violation specification. Our behaves functionally formally equivalent hardware description language (HDL) specification throughout entire FPGA flow, until is written by place-and-route tool...