A5024461213- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Real-Time Systems Scheduling
- Formal Methods in Verification
- Model-Driven Software Engineering Techniques
- Manufacturing Process and Optimization
- Radiation Effects in Electronics
- Advanced Software Engineering Methodologies
- Distributed and Parallel Computing Systems
- VLSI and Analog Circuit Testing
- Real-time simulation and control systems
- Simulation Techniques and Applications
- VLSI and FPGA Design Techniques
- Cognitive Computing and Networks
- Mechatronics Education and Applications
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Experimental Learning in Engineering
- Flexible and Reconfigurable Manufacturing Systems
- Advanced Computational Techniques and Applications
- Ferroelectric and Negative Capacitance Devices
- Modeling and Simulation Systems
- Mathematical Control Systems and Analysis
- Image Processing Techniques and Applications
KTH Royal Institute of Technology
2016-2025
GMV Innovating Solutions (Spain)
2016
Kista Photonics Research Center
2013
Information Technology Institute
2008
The scope of the formal system design (ForSyDe) methodology is high-level modeling and refinement systems-on-a-chip embedded systems. Starting with a specification model, that captures functionality at high abstraction level, it provides design-transformation methods for transparent process model into an implementation optimized synthesis. main contribution this paper ForSyDe technique treatment transformational refinement. We introduce constructors, cleanly separate computation part from...
Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete synchronous untimed MoCs distinguished. System level models serve a variety objectives partially contradicting requirements. Consequently, it is argued that different necessary for various tasks phases in design an embedded system. Moreover, have be integrated provide coherent system modelling analysis environment. The relation between some popular languages...
Raising the level of abstraction is considered key to addressing ever-increasing complexity embedded system design, but it causes additional challenges due larger gap between initial specification and final implementation. This paper addresses current lack systematic design methods by extending existing design-transformation-based approaches wrapping them into a rule-based transformational methodology for heterogeneous multi-processor platforms. The cross-fertilizes with program...
Small satellites empower different applications for an affordable price. By dealing with a limited capacity using instruments high power consumption or data-rate requirements, small satellite missions usually focus on specific monitoring and observation tasks. Considering that multispectral hyperspectral sensors generate significant amount of data subjected to communication channel impairments, bandwidth constraint is important challenge in transmission. That issue addressed mainly by source...
Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining formal base form SDF graphs with predictable platforms providing guaranteed QoS, paper proposes flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on shared platform. The formulated declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping scheduling application...
The feasibility of a message in network concerns if its timing property can be satisfied without jeopardizing any messages already the to meet their properties. We present novel analysis for real-time (RT) and nonreal-time (NT) wormhole-routed networks on chip. For RT messages, we formulate contention tree that captures contentions network. coexisting NT propose simple bandwidth partitioning method allows us analyze independently.
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public domain simulators Sim-Panalyzer and Cacti are used estimate dissipations of parameterized architectural components. As main contributions, schedule multi-clock synchronous modeling framework, guarantee application timing properties by analysis, customize both processor voltage-frequency levels memory sizes in...
We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize buffer requirement for with throughput guarantees. A novel declarative way constraint based SW/HW systems proposed, while application guaranteed by periodic phases in execution. use voice-band modem exemplify capabilities our method. experimental results show advantages techniques both less and higher guarantees compared traditional PAPS
SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. synthesizes terms of pre-characterized function (FIMPs). It explores the design space three dimensions, number FIMPs, type FIMPs and pipeline parallelism between producing consuming FIMPs. We introduce timing interface model to enable reuse automatic generation Global Inter-connect Control (GLIC) glue together working system. has...
Emerging architectures such as partially reconfigurable FPGAs provide a huge potential for adaptivity in the area of embedded systems. Since many system functions are only executed at particular points time they can share an adaptive component with other functions, which significantly reduce design costs. However, adds another dimension complexity into since behaviour changes during course adaptation. This imposes additional requirements on process, verification. In this paper we illustrate...
When targeting an OpenCL application to platforms with multiple heterogeneous accelerators, task tuning and mapping have cope device-specific constraints. To address this problem, we present innovative design flow for the customization performance optimization of applications on parallel platforms. It consists two phases: 1) a phase that optimizes each kernel given platform 2) task-mapping maximizes overall throughput by exploiting concurrency in graph. The is suitable customizing...
We present a flexible method for bus and network on chip performance analysis, which is based the adaptation of workload models to resemble various applications. Our analysis assists in selection communication infrastructure early design process. The uses (1) synthetic are similar timed Petri nets (2) b-model self-similar workloads. This allows exploration larger portions space than possible with traditional stochastic models. illustrated tutorial examples where both NoC platform analyzed
We propose a novel heterogeneous model-of-computation (HetMoC) framework in SystemC for embedded computing systems. As the main contribution, we formally define computation and communication multiple domains (continuous-time, discrete-event, synchronous/reactive, untimed) as polymorphic processes signals, present domain interfaces to integrate different together process networks. Especially, continuous-time signals are defined with time continuum, which distinguished from existing...
When designing complex mixed-critical systems on multiprocessor platforms, a huge number of design alternatives has to be evaluated. Therefore, there is need for tools which systematically find and analyze the ample identify solutions that satisfy constraints. The recently proposed space exploration (DSE) tool DeSyDe uses constraint programming (CP) implementations with performance guarantees multiple applications potentially constraints shared platform. A key component its throughput...
Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining formal base form SDF graphs with predictable platforms providing guaranteed QoS, paper proposes flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on shared platform. The formulated declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping scheduling application...
SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. synthesizes terms of pre-characterized function (FTMPs). It explores the design space three dimensions, number FTMPs, type FTMPs and pipeline parallelism between producing consuming FTMPs. We introduce timing interface model to enable reuse automatic generation Global Interconnect Control (GLIC) glue together working system. has...
We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based optimized computation and contention-free routing. The of processors computing communication transactions are formulated as constraint problem, to avoid the overhead in TDMA-like heuristic schemes. A public domain solver is exploited solve NP-complete efficiently, together with problem specific modeling techniques. Experimental results show that proposed can achieve high...
New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code IP models in order be accepted the industry. To tackle this problem, we introduce concept of wrappers context formal heterogeneous embedded system framework. The formalism is based on language-independent computation. Wrappers enable framework co-simulate/co-execute with external which might code, an block, or implementation partially refined system. They defined formally keep...
Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none available CP consider tradeoff between throughput buffer requirements or power...