Xavier Cauchy

ORCID: 0000-0003-2424-5056
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About
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Research Areas
  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis
  • Silicon and Solar Cell Technologies
  • 3D IC and TSV technologies
  • Advanced Sensor and Energy Harvesting Materials
  • Lightning and Electromagnetic Phenomena
  • Advanced Surface Polishing Techniques
  • Combustion and Detonation Processes
  • Electron and X-Ray Spectroscopy Techniques
  • Advanced Materials and Mechanics
  • Nanopore and Nanochannel Transport Studies
  • Thin-Film Transistor Technologies
  • Additive Manufacturing and 3D Printing Technologies
  • Electrical Fault Detection and Protection
  • Fire dynamics and safety research
  • Metallurgy and Material Science
  • Electrodeposition and Electroless Coatings
  • Nuclear Physics and Applications
  • Environmental and Industrial Safety
  • Carbon Nanotubes in Composites
  • Ion-surface interactions and analysis
  • Nanoparticles: synthesis and applications
  • Supercapacitor Materials and Fabrication
  • Electromagnetic wave absorption materials

Polytechnique Montréal
2015-2019

Soitec (France)
2010-2013

Université de Montréal
2013

Three-dimensional (3D) printing with conductive polymer nanocomposites provides an attractive strategy for the "on-demand" fabrication of electrical devices. This paper demonstrates a family highly multimaterial composites that can be directly printed into ready-to-use multifunctional devices using flexible solvent-cast 3D technique. The new material design leverages high aspect ratio and low contact resistance hybrid silver-coated carbon nanofibers (Ag@CNFs) excellent printability...

10.1021/acsami.9b04245 article EN ACS Applied Materials & Interfaces 2019-06-12

Noble-metal-coated carbon-based nanoparticles, when used as electrically conductive fillers, have the potential to provide excellent conductivity without high weight and cost normally associated with metals such silver gold. To this effect, many attempts were made deposit uniform metallic layers on core nanoparticles an emphasis for its conductivity. The results so far disheartening metal morphology being better described a decoration than coating small effects electrical of bulk particles....

10.1021/acsami.7b06526 article EN ACS Applied Materials & Interfaces 2017-07-14

The Ultra-Thin SOI and BOX substrates are the foundation of Fully Depleted planar technology, a CMOS scaling solution for 20 nm node beyond. Using Smart CutTM UTSOI development, with & thickness reduced down to 12 25 respectively, is on way High Volume Manufacturing by end 2011. To improve device Vt variation control, total layer less than +/- 1 all measured points preproduction wafers already achieved 0.5 targeted. Tight at scale also demonstrated.

10.1149/1.3570801 article EN ECS Transactions 2011-04-25

Polymeric composite materials are now very well established in all areas of engineering and still increasingly being used to replace metallic counterparts. As an important advantage, hold the promise multifunctionality, that is, fine tuning material composition synthetically achieve specific requirements. Among these requirements, electrical conductivity is limited values orders magnitude below those typical metals. An approach conductive fillers, which involves taking advantage favorable...

10.1002/adem.201800541 article EN Advanced Engineering Materials 2018-09-13

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one key criteria to control Vt variation planar FDSOI devices. We present an evolutionary approach SmartCut™ technology which already allows achieving a maximum total layer thickness less than ± 10 Å on preproduction volume. Total 5 targeted.

10.1109/icicdt.2011.5783188 article EN 2011-05-01

UTBOX25 substrates are now ready for high volume manufacturing, as first substrate of choice planar Fully- Depleted technology. Smart CutTM technology demonstrates its capability to provide ultra thin SOI & BOX layers with extremely tight thickness control low ± 5 Aå. Substrates support scaling down 11 nm node, including strained SOI, under development and results presented

10.1149/1.3700957 article EN ECS Transactions 2012-04-27

Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong emphasis has been put on layer thickness control low stress variation. A 1.2 Å RMS roughness less than 10% fluctuation already demonstrated sSOI wafers.

10.1109/icicdt.2012.6232869 article EN 2012-05-01

Devices using fully depleted undoped channels are among the most promising candidates for next device generations due to their better immunity short channel effects (SCE) (1) and random dopant fluctuation. Channel engineering control then critical as silicon thickness fluctuation is a statistical source of VT variability strained provide 47% increase in drive current NFETs (2) without any degradation PFETs (3). SOI substrates from Soitec complete set manufacturing solutions either planar or...

10.1149/05005.0053ecst article EN ECS Transactions 2013-03-15

Views Icon Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Twitter Facebook Reddit LinkedIn Tools Reprints and Permissions Cite Search Site Citation Xavier Cauchy, Sjoerd Roorda; Nearly equidistant single swift heavy ion impact sites through nanoporous alumina masks. AIP Conf. Proc. 19 April 2013; 1525 (1): 375–379. https://doi.org/10.1063/1.4802354 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks...

10.1063/1.4802354 article EN AIP conference proceedings 2013-01-01

Abstract not Available.

10.1149/ma2012-02/32/2634 article EN Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) 2012-06-04

Ultra-thin SOI wafer technologies designed for 22/20nm CMOS are presented. It is stressed that planar, non-doped, and fully-depleted (FD) structures realistic options not only solve various scaling issues, but also provide simplicity flexibility in the device process circuit design. To realize planar FD-SOI CMOS, 300mm by Smart Cut™ [1] has been optimized, focusing on uniformity of Si film thickness, adjusting thickness buried oxide (BOX). shown variation a 12nm-thick can be controlled...

10.1109/icsict.2010.5667514 article EN 2010-11-01

Abstract not Available.

10.1149/ma2011-01/23/1448 article EN Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) 2011-03-01

Substrate engineering using Smart Cut <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> and Stacking for advanced LSIs is overviewed. For digital CMOS applications, planar fully-depleted (FD) SOI structure provides a realistic solution to bridge the technology gap between bulk three-dimensional FD structures. Production of FD-SOI will be started soon in 28nm technology. RF on other hand, are areas where substrate bringing unique values...

10.1109/icsict.2012.6467819 article EN 2012-10-01
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