A5077958041- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Drilling and Well Engineering
- Ferroelectric and Negative Capacitance Devices
- Hydrocarbon exploration and reservoir analysis
- Hydraulic Fracturing and Reservoir Analysis
- Advanced Data Storage Technologies
- CO2 Sequestration and Geologic Interactions
- Geological Modeling and Analysis
- Nuclear Physics and Applications
- Structural Integrity and Reliability Analysis
- Hydrogen embrittlement and corrosion behaviors in metals
- Enhanced Oil Recovery Techniques
- Offshore Engineering and Technologies
- Laser-Plasma Interactions and Diagnostics
- Ion-surface interactions and analysis
- Rock Mechanics and Modeling
- Lattice Boltzmann Simulation Studies
- Seismic Imaging and Inversion Techniques
- Quantum and electron transport phenomena
- Geotechnical and Geomechanical Engineering
- Reservoir Engineering and Simulation Methods
- Silicon Carbide Semiconductor Technologies
The University of Texas at Austin
1998-2024
Bureau of Economic Analysis
2014-2024
Summary Segmentation of high-resolution X-ray microcomputed tomography (µCT) images is crucial in digital rock physics (DRP), affecting the characterization and analysis microscale phenomena porous media. The complexity geological structures nonideal scanning conditions pose significant challenges to conventional image segmentation approaches. Motivated by recent increasing popularity deep learning (DL) techniques processing, this work undertakes a comparative study DL models, specifically...
In this paper, models appropriate for device simulators are developed which account the quantum mechanical nature of accumulated regions. Accumulation layer quantization is important in deep submicron (/spl les/0.25 /spl mu/m) MOS devices overlapped source/drain extension regions, accumulation mode SOI devices, and buried-channel PMOS structures. Computationally efficient suitable routine simulation presented that predict reduction net electron (hole) sheet charge when region accounted for....
High permittivity (K) gate insulators are projected for sub-100 nm Si MOSFETs since direct tunneling will likely limit SiO/sub 2/ thicknesses to 1.0-1.5 nm. High-K avoid tunneling, but their larger physical introduce subtle capacitive coupling phenomena such as fringing-induced barrier lowering (FIBL) that can compromise off-state leakage. In this study, device simulation examines both on and drain current with very high-K sidewall spacers reveal new source-side boundary condition effects....
A multiple-stage simulation procedure identifies, for the first time, location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The method incorporates both electron and hole Monte Carlo analysis to calculate this current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues increase smaller channel length (50/spl times/ from L/sub g/-03.39 0.12 /spl mu/m) higher substrate doping (more than 6/spl when doubled) scaled, low-power memory.
The need to understand and predict MOS accumulation layer mobility has become increasingly important as devices scale the 100 nm gate length range. Indeed, in shallow source/drain extension MOSFETs is becoming a significant part of series resistance. Also, major carrier transport mode SOI PMOS buried-channel MOSFETs. However, temperature dependent experimental data accurate models for are not available. This paper reports first time both electrons holes. Also time, we report holes over range...