A5101917099- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Energy Harvesting in Wireless Networks
- Wireless Body Area Networks
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Bluetooth and Wireless Communication Technologies
- Wireless Power Transfer Systems
- Advanced Adaptive Filtering Techniques
- Semiconductor Lasers and Optical Devices
- Advanced Power Amplifier Design
- Ultra-Wideband Communications Technology
- CCD and CMOS Imaging Sensors
- Structural Health Monitoring Techniques
- Neuroscience and Neural Engineering
- Advanced MIMO Systems Optimization
- Metallurgy and Material Forming
- Microstructure and mechanical properties
- Power Line Communications and Noise
- Advanced Memory and Neural Computing
- Mechanical and Optical Resonators
- ECG Monitoring and Analysis
- Molecular Communication and Nanonetworks
- Microwave Engineering and Waveguides
Imec the Netherlands
2014-2024
Nanjing University of Aeronautics and Astronautics
2021
Holst Centre (Netherlands)
2012-2019
Eindhoven University of Technology
2012-2018
Zhejiang Water Conservancy and Hydropower Survey and Design Institute
2011
This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP transceiver is one of the most critical components that enables these emerging applications, as it can consume up to 90% total battery energy. Furthermore, a low-cost radio design with area-efficient fully integrated important...
A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals settling facilitates calibration. two-mode 0.3 fF capacitors reduce power area. The can directly detect the sign of dynamic error correct both them simultaneously in stepwise feedback loop. achieves 20 dB spur reduction little area overhead. chip implemented 40 nm CMOS consumes 46 μW from 1 V supply, 64.1 SNDR FoM 5.5 fJ/conversion-step at Nyquist.
The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals advent new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates power consumption in nodes, thus low-power transceivers are desired. Most state-of-the-art support only proprietary modes with OOK FSK modulations, and have poor sensitivity low data rate [1,2]. In this work, 15.6-compliant transceiver enhanced...
This paper presents an ultra-low power wireless transceiver specialized for but not limited to medical implantable applications. It operates at the 402-405-MHz implant communication service band, and also supports 420-450-MHz industrial, scientific, band. Being IEEE 802.15.6 standard compliant with additional proprietary modes, this highly configurable achieves date rates from 11 kb/s 4.5 Mb/s, which covers requirements of conventional The phase-locked loop-based transmitter architecture is...
Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent efficiency. However, intrinsic accuracy (DAC matching) limited up to 10 12b in modern CMOS technologies [1]. Scaling the device dimensions can improve matching but it deteriorates power-efficiency speed. Alternatively, calibrations [2-5] are introduced correct errors (e.g., comparator offset capacitor mismatch) push SNDR beyond 62dB....
This paper presents a low-voltage (0.8V) ultra-low-power Bluetooth 5(BT5)/Bluetooth Low Energy(BLE) digitally-intensive transceiver for IoT applications. In comparison to BLE, BT5 has 2x higher data-rate and 4x longer range, while having >8x packet. The BLE prior arts [1-5] have made significant efforts minimize the power consumption battery life, as well chip area. However, prior-art Cartesian radios consume namely 6 10mW [1-3] achieve <;-94dBm sensitivity but with relatively high supply...
The recent popularity of indoor-localization applications such as secure access and asset tracking has led to growing interest in accurate RF-based ranging solutions. Impulse-radio ultra-wideband (IR-UWB) is a promising solution for due its wideband 0peration. recently released IEEE 802. 15.4z standard [1] improves upon the security mandates coherent operation with higher mean pulse-repetition frequencies (mPRF), comparison legacy 15.4a. next generation IR-UWB devices demand ultra-low-power...
In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven uses topdown approach and generates circuits from specification to layout automatically. A introduced different of SAR ADC: fully synthesized control logic; script-based flow combining equations, library, templatebased the digital-to-analog converter; lookup table combined with...
Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce overall system power consumption [1]. This requires swift start-up behavior of transceiver. The crystal oscillator (XO) generates a stable reference clock for PLL synthesize carrier and derive clocks all other parts transceiver SoC, e.g., ADC digital baseband. typical time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired standard-compliant transmitter, the proposed method minimizes overhead system power, area complexity. The 2-dimensional pattern reduces latency of event below 100μs. Supplied at battery voltage 2V, chip integrates power management unit, offset noise...
An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and fully-digital polar transmitter is presented. For the receiver, current-mode front-end covers mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains bandwidths an automatic gain/DC-offset calibration. Implemented in 40nm CMOS 1V supply, this -104dBm sensitivity 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils adjacent channel rejection requirements at least 17dB...
Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular respiratory diseases. However, a sensing IC must consume ultra-low power under sub-volt supply to comply with miniaturized batteries. This work presents 0.6 V analog frontend (AFE) consisting an instrumentation amplifier (IA), current source (CS) SAR ADC. The AFE can measure ECG BioZ simultaneously single IA by employing...
Using IR-UWB for accurate battery-powered localization requires low energy consumption and high interference resilience. The presented 802.15.4z transceiver features power thanks to its inverter-based RX architecture polar TX. two-stage distributed PLL enables simultaneous multi-channel reception, reducing the measurement time of localization. It consumes 8.9mW in TX mode 21.5mW/ch. while achieving -33dBm OOB blocker tolerance.
This paper presents a millimeter-scale crystal-less wireless transceiver for volume-constrained insertable pills. Operating in the 402-405 MHz medical implant communication service (MICS) band, phase-tracking receiver-based over-the-air carrier recovery has ±160 ppm coverage. A fully integrated adaptive antenna impedance matching solution is proposed to calibrate variation inside body. tunable network (TMN) with single inductor performs both transmitter (TX) and receiver (RX) TX/RX mode...
A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. self-biased ΣΔ digitally controlled oscillator (DCO) locked to an RC time constant via single-bit chopped comparator and digital filter. Such highly digitized architecture fully exploits the advantages of advanced processes, thus enabling operation down 0.7 V small area (0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled oscillator using the proposed startup technique in 90-nm CMOS presented. Thanks dynamically adjusted load, negative resistance boosted, achieving a 13× time reduction and an 95μW 24-MHz at 1 V. fully autonomous feedback loop detects envelop adjusts load capacitance start-up. low-power...
This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased ΣA Digitally Controlled Oscillator (DCO) is locked to an RC time constant via feedback loop consisting of single-bit chopped comparator and digital filter, thus maximizing the use circuits while keeping only network as sole analog blocks. Analysis behavior level simulations DFLL have been carried out guide optimization...
A 0.8-V Bluetooth 5 (BT5) digitally intensive transceiver with a phase-tracking RX and digital TX in 40-nm CMOS is presented. For the RX, hybrid loop filter loop-delay compensation proposed to suppress controlled oscillator (DCO) sidelobe energy, enhancing interference resilience. To facilitate DCO-based for reception of BT5 signals, corresponding baseband implemented carrier frequency offset (CFO) calibration remove initial static CFO error during preamble, while an automatic tackles drift...
This paper presents an event-driven neuromorphic sensing system capable of performing on-chip feature extraction and "send-on-delta" transmission for insertable cardiac monitoring. A background offset calibration improves the SNDR clockless level-crossing ADCs. fully synthesized spiking neural network extracts full ECG PQRST features with $\lt 1$ ms time precision. An body channel communication minimizes energy. The prototype is fabricated in 40nm CMOS consumes $28.2 \mu \mathrm{W}$ power.
The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. digital-to-time converter (DTC) is the key enabler but nonlinearity can easily create fractional spurs. This paper analyzes effect of DTC on in-band spurs and proposes method to characterize it in built-in fashion by means fine-resolution ΔΣ TDC that forms an outer loop with DTC. realized 40nm CMOS exhibits only 1.8ps rms random jitter.
A WiFi (IEEE 802.11g) and BLE combo transmitter (TX) for IoT applications is presented. wideband digital polar architecture consisting of an all-digital PLL-based frequency modulator a switched-capacitor digitally-controlled PA achieves optimal energy efficiency both BLE. The dynamic FM correction AM alias suppression techniques are applied to support 20MHz 802.11g. Implemented in 28nm CMOS technology with 0.9V supply, this highly reconfigurable TX -22dB EVM 802.11g up MCS4 1.6% FSK error...
An on-chip DFLL (Digitally Frequency Locked Loop) based wakeup timer with a time-domain trimming featuring an embedded temperature sensor is presented. The proposed exploits the deterministic characteristics of two complementary resistors and results in fine step (±1ppm), allowing small frequency error after (<; ±20ppm). sensing running background negligible power (2%) hardware overhead 1%). chip fabricated 40nm CMOS, consumes 380nW, resulting 0.9pJ/cycle energy efficiency while achieving...
Nowadays, almost every mobile device features Bluetooth Low Energy (BLE) connectivity. Accurate RF-based ranging is of major importance to enable rapidly emerging applications such as indoor localization and navigation, asset tracking well secure access control. Phase-based has many advantages over other methods Time-of-Flight or signal-strength-based approaches [1]. based on the phase difference between two nodes, which depends RF frequency. To mitigate multipath problems deal with 2n...