A5059769555- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
- Interconnection Networks and Systems
- Structural Analysis and Optimization
- Embedded Systems Design Techniques
- Aeroelasticity and Vibration Control
- Advanced Materials and Mechanics
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- VLSI and FPGA Design Techniques
- Electromagnetic Compatibility and Noise Suppression
- Microgrid Control and Optimization
- Composite Structure Analysis and Optimization
- Advancements in Semiconductor Devices and Circuit Design
- Modular Robots and Swarm Intelligence
- Embedded Systems and FPGA Design
- 3D IC and TSV technologies
- Statistics Education and Methodologies
- Radiation Effects in Electronics
- Optimal Power Flow Distribution
- Power System Optimization and Stability
- Copper Interconnects and Reliability
- Advanced Battery Technologies Research
- Electrostatic Discharge in Electronics
Poughkeepsie Public Library District
2002-2025
Durham University
2023
University of Limerick
2019-2021
IBM (United States)
2007-2014
IBM Research - Thomas J. Watson Research Center
2002
Voltage noise characterization is an essential aspect of optimizing the shipped voltage high-end processor based systems. noise, i.e. Variations in supply due to transient fluctuations on current, can negatively affect robustness design if it not properly characterized. Modeling and estimation a pre-silicon setting typically inadequate because difficult model chip/system packaging power distribution network (PDN) parameters very precisely. Therefore, systematic, direct measurement-based...
This paper describes the design methodology employed in of S/390® Parallel Enterprise Server G4 microprocessors. Issues verifying metrics area, power, noise, timing, testability, and functional correctness are discussed within context a transistor-level custom approach. Practical issues managing complexity 7.8-million-transistor encouraging productivity introduced.
This paper describes the circuit and physical design features of z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order cores, running at 5.2 GHz, on die with an area 512 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> containing estimated 1.4 billion transistors. core methodology specific are presented, focusing techniques used to enable high-frequency operation. In addition, power,...
The microprocessor chip for the IBM zEnterprise 196 (z196) system is a high frequency, high-performance design that adds support out-of-order instruction execution and increases operating frequency by almost 20% compared to previous 65nm design, while still fitting within same power envelope. Despite many difficult engineering hurdles be overcome, team was able achieve product of 5.2GHz, providing significant per formance boost new system.
This work describes the circuit and physical design implementation of processor chip (CP), level-4 cache (SC), multi-chip module at heart EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. CP contains 6 super-scalar, out-of-order cores, running 5.5 GHz, while SC 192 MB eDRAM cache. Six two are mounted on a glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects explored detail, with most focus...
The next-generation System z design introduces a new microprocessor chip (CP) and system controller (SC) aimed at providing substantial boost to maximum capacity performance compared the previous zEC12 in 32nm [1,2]. As shown die photo, CP includes 8 high-frequency processor cores, 64MB of eDRAM L3 cache, interface IOs ("XBUS") connect two other chips L4 cache chip, along with memory interfaces, 2 PCIe Gen3 an I/O bus (GX). is implemented on 678 mm <sup...
The power management strategy adopted for the IBM z13™ processor chip (referred to as CP or Central Processor chip) is guided by three basic principles: (a) controlling peak consumption setting a realistic limit on so-called thermal design point (TDP) driven customer workloads and maximum-power stress microbenchmarks; (b) reduction of voltage margin using novel dynamic guard-banding technique; (c) creation rich new set fine-grained, time-synchronized sensors that track performance, power,...
The new System z microprocessor chip ("CP chip") features a high-frequency processor core running at 5.5GHz in 32nm high-κ CMOS technology [1], using 15 levels of metal. This is successor to the 45nm product [2], with significant improvements made and nest (i.e. logic external cores) order increase performance throughput design. Also, special considerations were necessary ensure robust circuit operation used for implementation. As seen die photo, contains 6 cores (compared 4 version), large...
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on supply noise mitigation techniques. With voltage scaling, very current draws, broad usage of clock gating, advanced solutions are needed for next-generation products to minimize droop response time, can be defined as the latency from when a dangerous begins until countermeasure is effective.
The IBM Z microprocessor in the z14 system has been redesigned to improve performance, capacity, and security [1] over previous z13 [2]. contains up 24 central processor (CP) 4 controller (SC) chips. Each CP, shown die photo A (Fig. 2.2.7), operates at 5.2GHz is comprised of 10 cores, 2 PCIe Gen3 interfaces, an IO bus (GX), 128MB L3 embedded DRAM (eDRAM) cache, X-BUS interfaces connecting other CP chips one SC chip, a redundant array independent memory (RAIM) interface. core on chip 4MB...
Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the circuits with delivery network (PDN) on chip, chip module, backplane, voltage regulator module (VRM). Traditionally, periodic square-wave activity patterns all cores in sync, which yield low-frequency (LF) or mid-frequency (MF) impedance peaks associated backplane chip/module, respectively, are considered to give rise worst case noise. However, droops both deeper faster at...
The G6 system is a sixth generation CMOS server for the S/390 line of products featuring 12+2 SMP size and significant frequency improvements obtained through use low-Vt devices copper interconnects. microprocessor operates at 760 MHz fast end process distribution. ships 637 in chilled configuration. Measured performance on 12 way 1600 MIPs, providing over 50% more than G5. This uses CMOS7S technology, which has 0.2 /spl mu/m process. chip 6 levels metal plus an additional layer local...
The IBM z14 is the latest update in storied history of mainframes. Reliability, availability, security, and scalability are foundation mainframe line. System reliability availability targets excess 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some many processes used to ensure that lifetime. An additional part power management (PM). 5.2-GHz high-power design central processor requires advanced on-die PM capabilities adapt intensive instruction...
Morphing technologies use large, seamless changes in the shape of a structure to enable multi-functionality and reconfigurability. Several industrial sectors could benefit from morphing structures, including medical, energy aerospace which require lightweight, simple reliable solutions. Composite materials are key lightweight due their increased strength- stiffness-to-mass ratios, stiffness tailorability excellent fatigue properties, all reduce mass complexity these types structures. By...
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and IEEE compliant binary floating-point. microprocessor operates at 600 MHz fast end process distribution, although shipped 500 in 10+2 SMP configuration. Measured performance on 10 way 1069 MIPs. This uses 0.25 mum process. chip 6 levels metal plus additional layer local interconnect 14.6times14.7 mm <sup...
The IBM z15 system improves upon the prior-generation z14 design within same chip footprint and technology node, while featuring addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well core features on-chip accelerators. largest 5-drawer configuration includes 20 central processor (CP) chips, five controller (SC) 40 TB memory. With ~200 cores across all CP chips operating with 99.99999% uptime at 5.2 GHz, achieves a 25% increase in capacity 14% single thread performance...
The two chips at the heart of IBM z13™ system include a processor chip (referred to as CP or Central Processor chip) and an L4 (Level 4) cache SC System Controller chip), each 678 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in area. were implemented with approximately 4 billion ( <inline-formula xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 \times 10^{9} $</tex-math></inline-formula> ) 7.1 transistors,...
Morphing composite structures offer lightweight, tunable stiff solutions to complex engineering problems, such as deployable spacecraft technology. Notably, the morphing cylindrical lattice is a multi-stable structure that can change from being compact when stowed long and thin deployed. This particularly suited for booms, solar arrays antennas due its packaging efficiency lightweight nature. Current analytical models of these types only accurately predict stability characteristics lattices...
Composite materials can enhance morphing and deployable structure capability due to their high degree of tailorability favourable stiffness- strength-to-weight ratios. One such structure, the bistable helical lattice, is augmented in current work. To date this type shows promise aerospace systems which require linear actuation. Herein, capabilities are enhanced by removing traditional mechanical fasteners at joints, replacing them with magnets allow detachment re-attachment a controlled,...
Deployable spacecraft technology should be both lightweight and compact for storage while also being rigid expansive once deployed. A new type of structure that can meet these requirements is the morphing cylindrical lattice. This multi-stable morph from a stowed state, to long slender deployed beam. It comprises narrow strips carbon fibre composite material, making it particularly suitable deployable booms, solar arrays antennae. While existing modelling techniques focus on predicting...
Cycle-time targets were set for the IBM System z9™ processor subsystem prior to building system, and achieving these was one of biggest challenges we faced during hardware development. In particular, although processor-subsystem cycle-time improvement driven primarily by technology migration from CMOS 9S (130-nm lithography) z990 10S0 (90-nm new cooling capability z9 resulted a direct implementation with very limited improvements. The higher device current leakage power associated migration,...
Morphing composite structures are of significant interest due to the fact that they exhibit superior mass-to-stiffness ratios and a large degree tailorability in comparison traditional materials structures. One such morphing structure is multistable cylindrical lattice. Current work introduces novel variable-topology mechanism it through use both permanent magnets electromagnets. By replacing set mechanical fasteners from central intersection lattice strips with bespoke controllable...