A5041464693- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Low-power high-performance VLSI design
- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- Education Systems and Policy
- EFL/ESL Teaching and Learning
- VLSI and Analog Circuit Testing
- VLSI and FPGA Design Techniques
- Algorithms and Data Compression
- Semiconductor materials and devices
- Analog and Mixed-Signal Circuit Design
- Copper Interconnects and Reliability
- Adventure Sports and Sensation Seeking
- Numerical Methods and Algorithms
- Multilingual Education and Policy
- 3D IC and TSV technologies
- Travel Writing and Literature
Poughkeepsie Public Library District
1997-2021
IBM (United States)
1999-2013
Network Technologies (United States)
2004
University of Tennessee at Knoxville
1949
The IBM S/390 G5 microprocessor in IBM's newest CMOS mainframe system provides more than twice the performance of previous generation, G4. offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic a redesigned L2 cache processor interconnect. implements ESA/390 instruction-set architecture, which is based on compatible original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing)...
The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache and integrated accelerators for decimal floating-point computation, cryptography, data compression. A separate SMP hub chip provides shared third-level interconnect fabric multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve 4.4-GHz system, pipeline that optimizes z10's CPU performance.
A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect. size 17.35 mm/spl times/17.30 mm about 7.8 million transistors. power supply 2.5 V measured dissipation 300 37 W. features two instruction units (IUs), fixed point (FXUs), floating (FPUs), buffer control element (BCE) unified 64-KB L1 cache, register...
The microprocessor chip for the IBM zEnterprise 196 (z196) system is a high frequency, high-performance design that adds support out-of-order instruction execution and increases operating frequency by almost 20% compared to previous 65nm design, while still fitting within same power envelope. Despite many difficult engineering hurdles be overcome, team was able achieve product of 5.2GHz, providing significant per formance boost new system.
The S/390® Parallel Enterprise Server Generation 4 processor is an implementation of the IBM ESA/390™ architecture on a single custom CMOS chip. It was designed blank slate after consideration remapping either prior design or bipolar design. uses straightforward pipeline both to achieve fast cycle time and speed cycle. complex instructions are implemented using highly privileged subroutines called millicode. To high data integrity while maintaining clock frequency, chip contains duplicate I-...
Even though decimal arithmetic is pervasive in financial and commercial transactions, computers are still implementing almost all calculations using binary arithmetic. As chip real estate becomes cheaper it becoming likely that more computer manufacturers will provide processors with engines. Programming languages databases expanding the data types available while there has been little change base hardware. a result, each language application defining different few have considered efficiency...
This work describes the circuit and physical design implementation of processor chip (CP), level-4 cache (SC), multi-chip module at heart EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. CP contains 6 super-scalar, out-of-order cores, running 5.5 GHz, while SC 192 MB eDRAM cache. Six two are mounted on a glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects explored detail, with most focus...
The new System z microprocessor chip ("CP chip") features a high-frequency processor core running at 5.5GHz in 32nm high-κ CMOS technology [1], using 15 levels of metal. This is successor to the 45nm product [2], with significant improvements made and nest (i.e. logic external cores) order increase performance throughput design. Also, special considerations were necessary ensure robust circuit operation used for implementation. As seen die photo, contains 6 cores (compared 4 version), large...
A microprocessor implementing IBM S/390 architecture operates in a system at up to 400 MHz (2.5 ns). The microprocessor, initially CMOS5X technology, migrated CMOS6S by shrinking the FET length dimensions but not interconnect dimensions. chip is 17.35/spl times/17.30 mm/sup 2/ with about 7.8M transistors. power supply 2.5 V and measured dissipation 300 37 W. features two instruction units, fixed point floating buffer control element, register unit. It dispatches one per cycle. PLL provides...
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and IEEE compliant binary floating-point. microprocessor operates at 600 MHz fast end process distribution, although shipped 500 in 10+2 SMP configuration. Measured performance on 10 way 1069 MIPs. This uses 0.25 mum process. chip 6 levels metal plus additional layer local interconnect 14.6times14.7 mm <sup...
IBM Z is both the oldest and among most modern of computing platforms. Launched as S/360 in 1964, mainframe became synonymous with large-scale for business remains workhorse enterprise businesses worldwide. Most world's largest banks, insurers, retailers, airlines, enterprises from many other industries have at center their IT infrastructure. This article presents an overview evolution microprocessors over past six generations. The discusses some underlying workload characteristics how these...
This article consists of a collection slides from the author's conference presentation on IBM's z6, next generation mainframe family microprocessor products. Some specific topics discussed include: special features, system specifications, and design for these products; architectures; applications use; platforms supported; processing capabilities; memory targeted markets.
The technical, business, and market requirements for large enterprise servers (“mainframes”) strongly influence the design of microprocessors these systems. Specific characteristics ESA/390 z/Architecture instruction set architectures lead to different pipeline branch prediction strategies than are found in most other microprocessors. robust, scalable performance across a wide range workloads, highly efficient logical partitioning, very high hardware reliability affect cache structure,...
The IBM z/Architecture™ instruction set architecture (ISA) is an extension of the Enterprise Systems Architecture/390® (ESA/390) ISA and features 64-bit general registers, operations, virtual real addressing. In addition, z/Architecture includes new instructions to optimize handling modern multi-byte character encodings improve performance programs written in high-level languages. It provides compatibility for ESA/390 application increases ease development programs. This paper presents...
The S/390 G4 CMOS processor is an implementation of the IBM ESA/390 architecture on a single custom chip. It new design which uses straightforward pipeline both to achieve fast cycle time and speed cycle. complex instructions are implemented using highly privileged subroutines called millicode. To high data integrity while maintaining clock frequency, chip contains duplicate I- E-units perform same operations each have their results compared.
The microprocessor revolution, of which this issue marks the 50th anniversary, drove remarkable innovations in instruction set architecture, microarchitecture, and system design, some continue to evolve current research commercial products. Many these features were indeed new, but others have their roots a line processor architectures that predates revolution that, alone among those ancient species, continues thrive modern information technology (IT) world: IBM mainframe, launched 1964 as...
The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on today's enterprise information technology systems, ranging from large data-intensive transaction processing to central unit-intensive business applications. Each these required innovations in design hardware, software, and instruction-set architecture (ISA) with coming several sources: out-of-order microprocessor core design, multilevel cache structure, new...
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