Spike-timing-dependent synaptic plasticity (STDP) is demonstrated in a synapse device based on ferroelectric-gate field-effect transistor (FeFET). STDP key of the learning functions observed human brains, where weight changes only depending spike timing pre- and post-neurons. The FeFET composed stacked oxide materials with ZnO/Pr(Zr,Ti)O3 (PZT)/SrRuO3. In FeFET, channel conductance can be altered density electrons induced by polarization PZT film, which controlled applying gate voltage...

This paper presents a SAR ADC with 71 dB SNDR and 85 SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase power, several SNR enhancement techniques are proposed. Firstly, the repeats comparison LSB by using redundant DAC to average comparator noise improve SNR. The technique also corrects settling error adaptively, which extends operation speed MHz even though extra period is added for averaging. Secondly, simple filtering method...

This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (Δ-Σ ADC) utilizing voltage controlled oscillator (VCO). The VCO, associated with pulse counter, works as high-speed quantizer. VCO quantizer also has function of first-order noise shaping because phase output is an integrated quantity input voltage. If maximum frequency (fvm) designed in range (2/sup bq/-2)fos < fvm bq/-1) fos and bq-bit counter used, multibit (bq-bit) can be realized, where...

This paper proposes an all-analog neural network LSI architecture and a new learning procedure called contrastive backpropagation learning. In analog LSI's with on-chip learning, inevitable offset errors that arise in the circuits seriously degrade performance. Using proposed here, are canceled to large extent effect of on performance is minimized. also describes prototype 9 neurons 81 synapses based which capable continuous neuron-state continuous-time operation because its fully parallel...

SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted GHz sampling range at low consumption. However, achieve SNR >70dB moderate speed, SARs still need a lot power, namely tens mW [1-2]. [1], very 90dB is achieved by stage amplify residue charge, which one reasons for 105mW consumption 12.5MS/s. [2], 8×...

Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-/spl mu/V 100-ps resolution substrate measurements of controlled noises a transition-controllable source and practical under operations. The dominated leaks supply/return bounce into the substrate, intensity determined transition activity, according to experimental observations. A time-series divided parasitic capacitance model derived as an efficient estimator supply current for...

In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). particular, a STDP symmetric function for the first time, and also demonstrate associative memory operation in Hopfield-type feedback network learning. our neuron model, information expressing processing results is given by relative timing of spike firing events. It well known that biological changes its weights STDP, provides learning rules...

This paper presents an ultra-low-power 2-step wake-up receiver for the IEEE 802.15.4g. The is composed of energy-detection (EDRX) and address-detection FSK (ADRX). ADRX activated only when EDRX detects a wakeup packet which minimizes power consumption. Fabricated in 65 nm CMOS process, achieves excellent sensitivity −87 dBm while consuming 45.5 µW average power.

Abstract Reservoir computing (RC) can efficiently process time-series data by mapping the input signal into a high-dimensional space via randomly connected recurrent neural networks (RNNs), which are referred to as reservoir. The representation of in reservoir simplifies subsequent learning tasks. Although this simple architecture allows fast and facile physical implementation, performance is inferior that other state-of-the-art RNN models. In study, improve ability RC, we propose...

A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This can generate substrate noises with controlled transitions size, interstage delay and direction for experimental studies on properties mixed-signal integrated circuit environment. Substrate measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift latch comparator direct probing PMOS follower. Measured waveforms indicate...

An oscillator array has been proposed for associative memory, in which the synchronization of multiple oscillators is utilized pattern-matching operations. input pattern represented by a set frequency shifts and matching result attributed to degree synchronization. Here, we propose an electrically coupled spin-Hall (SHO) SHOs exhibit interacting with each other through self-feedback spin torques. We numerically demonstrate functionality SHO array.

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in form of spikes. SNNs expected provide not only new machine-learning algorithms but also energy-efficient computational when implemented very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for based on temporal coding. A spiking neuron is designed facilitate analog VLSI implementations resistive memory, by which ultrahigh...

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> ) and charge-pump (CP) current over C (I xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> /C), SSCG can realize not only but also process independence at each operating frequency. The innovative point...

This paper proposes an algorithm for detecting bicycles on the road from a sequence of images acquired by stationary video camera. is suitable monitoring traffic situation safety, our includes shape-based object detection using HOG and SVM relative motion leg movements in bicycle pedaling. The movement, which can be achieved spatiotemporal 3D Gabor filtering, discriminate similar objects such as motorbikes.

Abstract A nanodisk array connected with a fin field-effect transistor is fabricated and analyzed for spiking neural network applications. This nanodevice performs weighted sums in the time domain using rising slopes of responses triggered by input spike pulses. The arrays, which act as resistance several giga-ohms, are self-assembly bio-nano-template technique. Weighted achieved an energy dissipation on order 1 fJ, where number inputs can be more than one hundred. amount orders magnitude...

A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed each layer summation results then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits implement Unlike conventional voltage or current mode circuits, use transient...

Bifurcation-diagram reconstruction estimates various attractors of a system without observing all them but only from several with different parameter values. Therefore, the bifurcation-diagram can be used to investigate how change values, especially for real-world engineering and physical systems which limited number observed. Although bifurcation diagrams have been reconstructed time-series data generated in numerical experiments, that targeted reconstructing time series measured phenomena...

Substrate crosstalk reduction is necessary for reliable high performance mixed signal LSI design. The paper demonstrates more than 67% as a consequence of supply bounce suppression.

Our team Hibikino-Musashi@Home was founded in 2010. It is based Kitakyushu Science and Research Park, Japan. Since 2010, we have participated the RoboCup@Home Japan open competition open-platform league every year. Currently, has 24 members from seven different laboratories Kyushu Institute of Technology. home-service robots are used as platforms for both education implementation our research outcomes. In this paper, introduce technologies that implemented robots.

Reservoir computing (RC) is a framework for constructing recurrent neural networks with simple training rule and sparsely randomly connected nonlinear units. The network (called reservoir) generates complex motion that can be used many tasks including time series generation prediction. We construct reservoir based on the dynamics of pseudo-billiard system produce in high-dimensional hypercube. In particular, we use chaotic Boltzmann machine (CBM) whose units exhibit behavior interact each...

Spiking neural networks (SNNs) more closely mimic the human brain than artificial (ANNs). For SNNs, time-to-first-spike (TTFS) encoding, which represents output values of neurons based on timing a single spike, has been proposed as promising model to reduce power consumption. Adversarial attacks that can lead ANNs misrecognize images have reported in many studies. However, characteristics TTFS-based SNNs trained using backpropagation algorithm against adversarial not yet clarified. In...

An isolation-merged vertical capacitor (IVEC) cell is described with emphasis on its scalability, simulated device characteristics and experimentally obtained oxide breakdown voltage. The IVEC size will be reduced to around 5 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by using the 0.5 rule process trench depth of 2.2 µm. Capacitor voltage nearly same conventional capacitor.

Analog CMOS circuit implementation of a system pulse-coupled phase oscillators is proposed. A that achieves the dynamics has been designed and fabricated using 0.25-µm technology. The proposed oscillator circuits with continuous-time operation interact each other via pulse at firing time. Update state achieved by integrating sensitivity function width time span. generated combination binary functions, while consists three-values {-1,0,1}. Introducing zero-value span in leads to fast...

An 11-b 300-MS/s double sampling pipelined ADC with on-chip digital calibration for memory effects is presented. In double-sampling architecture, effect of residual charge occurs due to sharing an op-amp between two channels ADC. The proposed foreground technique removes the error in domain without additional analog circuit. Thus, simplifies circuits, which extends operation speed over 300 MHz. chip fabricated a 40 nm CMOS and occupies 0.42 mm <sup...