A5076432415- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Cloud Computing and Resource Management
- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- Low-power high-performance VLSI design
- IoT and Edge/Fog Computing
- Distributed and Parallel Computing Systems
- Software System Performance and Reliability
- VLSI and FPGA Design Techniques
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Advanced Neural Network Applications
- Semiconductor materials and devices
- ECG Monitoring and Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- EEG and Brain-Computer Interfaces
- Distributed systems and fault tolerance
- Diabetic Foot Ulcer Assessment and Management
- Scientific Computing and Data Management
- Pressure Ulcer Prevention and Management
- Particle Accelerators and Free-Electron Lasers
- CCD and CMOS Imaging Sensors
- Real-Time Systems Scheduling
National Technical University of Athens
2016-2025
Harokopio University of Athens
2020-2023
Institute of Communication and Computer Systems
2010-2022
Politecnico di Milano
2013-2015
Anna Needs Neuroblastoma Answers
2015
National and Kapodistrian University of Athens
2007-2014
Healthcare is one of the most rapidly expanding application areas Internet Things (IoT) technology. IoT devices can be used to enable remote health monitoring patients with chronic diseases such as cardiovascular (CVD). In this paper we develop an algorithm for ECG analysis and classification heartbeat diagnosis, implement it on IoT-based embedded platform. This our proposal a wearable diagnosis device, suitable 24-hour continuous patient. We use Discrete Wavelet Transform (DWT) analysis,...
With the proliferation of portable and mobile IoT devices their increasing processing capability, we witness that edge network is moving to gateways smart devices. To avoid Big Data issues (e.g. high latency cloud based IoT), captured data starting from node. However, available capabilities energy resources are still limited do not allow fully process on-board. It calls for offloading some portions computation gateway or servers. Due bandwidth gateways, choosing levels connected allocating...
Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. We prove in mathematically rigorous manner that perforation, imposed errors are bounded and predictable, depending only input distribution. Through extensive experimental...
In this article, we target approximate computing for arithmetic circuits, focusing on the most complex and power-hungry units: hardware multipliers. Driven by lack of a clear solution energy-error efficiency existing multiplication techniques, present new, efficient, easily applied approximation design, as well explore current state-of-the-art design space. We show that proposed scheme can be equally at time to enable synthesis customized multiplier circuits runtime support dynamic tuning...
Supervised high-level synthesis (HLS) is a new class of design problems where exploration strategies play the role supervisor for tuning an HLS engine. The complexity problem increased due to large set tunable parameters exposed by “new wave” tools that include not only architectural alternatives but also compiler transformations. In this paper, we developed novel approach, called spectral-aware Pareto iterative refinement, exploits response surface models (RSMs) and spectral analysis...
Internet-of-Things (IoT) envisions an infrastructure of ubiquitous networked smart devices offering advanced monitoring and control services. Current art in IoT architectures utilizes gateways to enable application-specific connectivity devices. In typical configurations, gateway is shared among several However, given the limited available bandwidth processing capabilities gateway, quality service (QoS) must be adjusted over time not only fulfill needs individual device users, but also...
Modern micro-service and container-based cloud-native applications have leveraged multi-tenancy as a first class system design concern. The increasing number of co-located services/workloads into server facilities stresses resource availability capability in an unconventional unpredictable manner. To efficiently manage resources such dynamic environments, run-time observability forecasting are required to capture workload sensitivities under differing interference effects, according applied...
Approximate computing appears as an emerging and promising solution for energy-efficient system designs, exploiting the inherent error-tolerant nature of various applications. In this paper, targeting multiplication circuits, i.e., energy-hungry counterpart hardware accelerators, extensive exploration error--energy trade-off, when combining arithmetic-level approximation techniques, is performed first time. Arithmetic-aware approximations deliver significant energy reductions, while allowing...
Approximate computing forms a promising paradigm shift for energy efficient design by aggressively decreasing power consumption of inherently error-tolerant applications. However, approximate architectures exacerbate the complexity due to diversity inexact techniques and their impact on final circuit implementations. In this brief, we introduce accelerator synthesis, which enables power-optimized circuits under error bound constraints, leveraging incorporation diverse multi-level techniques....
Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, logic and circuit level, to low approximate arithmetic architectures hardware multipliers. Motivated from limited savings that approximation techniques can achieve in isolation, explore hybrid methods apply simultaneously more than one different layers. We introduce concept of...
The power-wall problem driven by the stagnation of supply voltages in deep-submicron technology nodes, is now major scaling barrier for moving towards manycore era. Although enables extreme volumes computational power, power budget violations will permit only a limited portion to be actually exploited, leading so called dark silicon. Near-Threshold voltage Computing (NTC) has emerged as promising approach overcome power-wall, at expenses reduced performance values and higher sensitivity...
Smith-Waterman algorithm is widely adopted by most popular DNA sequence aligners. The inherent computational intensity and the vast amount of NGS input data it operates on, create a bottleneck in genomic analysis flows for short-read alignment. FPGA architectures have been extensively leveraged to alleviate problem, each one adopting different approach. In existing solutions, effective co-design alignment still remains an open issue, mainly due narrow view on real integration aspects, such...
The increasing popularity of LLM-based chatbots combined with their reliance on power-hungry GPU infrastructure forms a critical challenge for providers: minimizing energy consumption under Service-Level Objectives (SLOs) that ensure optimal user experience. Traditional optimization methods fall short LLM inference due to autoregressive architecture, which renders them incapable meeting predefined SLO without <italic xmlns:mml="http://www.w3.org/1998/Math/MathML"...
EVOLVE is a pan European Innovation Action that aims to fully-integrate High-Performance-Computing (HPC) hardware with state-of-the-art software technologies under unique testbed, enables the convergence of HPC, Cloud and Big-Data worlds increases our ability extract value from massive demanding datasets. EVOLVE's advanced compute platform combines HPC-enabled capabilities, transparent deployment in high abstraction level, versatile processing stack for end-to-end workflows. Hence, domain...
This paper presents a methodology for fast and efficient Design Space Exploration during High Level Synthesis. An augmented instance of the design space is studied taking under consideration effects both compiler- architectural-level transformations onto final datapath. A new gradient-based pruning technique has been developed, which evaluates large portions solution in quick manner. At second level, proposed combined with exhaustive exploration order to guarantee quality solutions. We show...
We address the problem of custom Dynamic Memory Management (DMM) in Multi-Processor System-on-Chip (MPSoC) architectures. Customization is enabled through definition a design space that captures global, modular and parameterized manner primitive building blocks multi-threaded DMM. A systematic exploration methodology proposed to efficiently traverse space. Customized Pareto DMM configurations are automatically generated development software tools implementing methodology. Experimental...
Today, video analytics are becoming extremely popular due to the increasing need for extracting valuable information from videos available in public sharing services through camera-driven streams. Typically, organized as a set of separate tasks, each which has different resource requirements (e.g., computational- vs. memory-intensive tasks). The serverless computing paradigm forms very promising approach mapping such types applications, it enables fine-grained deployment and management...
This paper presents a new methodology for the synthesis of high performance flexible datapaths, targeting computationally intensive digital signal processing kernels embedded applications. The proposed is based on novel coarse-grained reconfigurable/flexible architectural template, which enables combined exploitation horizontal and vertical parallelism along with operation chaining opportunities found in application's behavioral description. Efficient techniques exploiting these optimization...
Very Long Instruction Word (VLIW) application specific processors represent an attractive solution for embedded computing, offering significant computational power with reduced hardware complexity. However, they impose higher compiler complexity since the instructions are executed in parallel based on static schedule. Therefore, finding a promising set of transformations and defining their effects have impact overall system performance. The proposed methodology provides designer integrated...
Approximate computing emerges as a new design paradigm for generating energy-efficient systems. Voltage overscaling (VOS) forms very promising technique to generate approximate circuits, and its application in cooperation other techniques is proven lead more efficient solutions. However, the existing tools fail provide effective voltage-aware simulation early exploration of power-error tradeoffs. In this brief, we propose VOSsim, framework that extends state-of-the-art industry strength...
The power-wall problem and its dual utilization-wall are considered among the main barriers to feasible/efficient scaling in manycore era. Several researchers have proposed usage of aggressive voltage techniques at near-threshold region, promising significant improvements power efficiency expense reduced performance values higher sensitivity process parametric variations. In this paper, we introduce a variability-aware framework for exploring potential power-efficiency Near Threshold...