A5000639997- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design
- Nanowire Synthesis and Applications
- Silicon Carbide Semiconductor Technologies
- Analog and Mixed-Signal Circuit Design
- Electrostatic Discharge in Electronics
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Microwave Engineering and Waveguides
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Advanced Power Amplifier Design
- Electromagnetic Compatibility and Noise Suppression
- Electrical and Bioimpedance Tomography
- Manufacturing Process and Optimization
- Distributed and Parallel Computing Systems
- Magnetic confinement fusion research
- Power Systems and Technologies
- Sensor Technology and Measurement Systems
- Ga2O3 and related materials
- Advanced Electrical Measurement Techniques
- Advanced MEMS and NEMS Technologies
- VLSI and FPGA Design Techniques
- Transition Metal Oxide Nanomaterials
École Polytechnique Fédérale de Lausanne
2002-2014
École Normale Supérieure - PSL
2014
Institution de Lavigny
2007-2010
Motorola (United States)
2004
The constant-current (CC) method uses a current criterion to determine the threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using same in both saturation and linear modes leads inconsistent results incorrect interpretation effects, such as drain-induced barrier lowering advanced CMOS...
In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap top gate (LG) and total back over channel region (LG + LIN). A potential well is created by biasing (VBG) in accumulation, while front (VFG) inversion. Holes from p+ source are injected forward-biased i junction stored...
This paper examines the relation between structure of a compact MOSFET model and its ability to harmonic distortion. It is found that non-singular behavior at zero drain bias essential for qualitatively correct simulations third power dependence. Specifically, nonlinear distortion analysis requires Gummel symmetry condition be satisfied by model. A simple procedure enforce without increasing complexity incorporated in an advanced surface-potential-based enable modeling.
This work proves the feasibility of electrically actuated, CMOS compatible, microwave VO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> switches on SiO /Si substrates with low variability, 100% yield, better than 109 cycles lifetime, ultra-steep OFF-ON transition and RF performance previously reported Al O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (flat -0.6 dB S xmlns:xlink="http://www.w3.org/1999/xlink">21-ON</sub> -10...
This paper presents a simple, physics-based, and continuous model for the quantum effects polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. analytical design-oriented MOSFET correctly predicts inversion depletion charges, transcapacitances, drain current, from weak to strong nonsaturation saturation. One single additional parameter is used polysilicon doping concentration, while correction does not introduce any new parameter. Comparison experimental data of...
There are several techniques for junction profiling available in literature, yet none of them practically suitable the accurate determination lateral steepness TFET devices, which is most important parameter influencing performance. In this work, a simple physics-based compact analytical model has been developed as function doping concentration and maximum electric field at junction. Using underlying physics, we report novel method to estimate using only <formula formulatype="inline"...
The semiconductor industry continues to grow and innovate; however, companies are facing challenges in growing their workforce with skilled technicians engineers. To meet the demand for well-trained workers worldwide, innovative ways attract talent strengthen local ecosystem of utmost importance. FOSS CAD/EDA tools combined free open-access PDKs can serve as a new platform bringing together IC design newbies, enthusiasts, experienced mentors.
In this paper, we report, for the first time, corner effect analysis in gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found accumulate and deplete more electrons than flat sides or channel center, when above (local accumulation) below depletion) flat-band voltage, respectively. On contrary inversion mode (IM) devices, there is no major contribution of corners current, therefore, device...
SUMMARY MOS‐Modelle und Parameterextraktion Arbeitskreis (MOS‐AK) is a European, independent compact modelling forum created by group of engineers, researchers and enthusiasts to promote advanced techniques model standardization using high‐level behavioural languages such as VHDL‐AMS Verilog‐A. This invited paper summarizes recent MOS‐AK open‐source activities presents topics in metal–oxide–semiconductor field‐effect transistor modelling, focusing particular on analogue/radio frequency...
In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-sectional cores on bulk substrate using optical lithography, hard mask/spacer technology, and local oxidation. ≈0.8 GPa uniaxial tensile stress was measured micro-Raman spectroscopy. The multigate show excellent electrical characteristics, e.g., 62 mV/decade 42% low-field electron mobility enhancement due to in comparison non-strained device, all at V <sub...
In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration local stressor technologies (both oxidation and metal-gate strain) to achieve ≥2.5 GPa uniaxial tensile stress is reported for the first time. deeply scaled shows low-field electron mobility 332 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V.s at room temperature, 32% higher than...
The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges micro- nano-meter CMOS processes. As present technologies continue geometry scaling designers can benefit using dedicated SPICE MOSFET models apply specific methodologies. EKV was developed especially to meet altogether analog/RF requirements. This paper describes a basic set DC parameter extraction...
In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 μm long suspended Si nanowire MOSFETs, highest process-based stress record MOSFETs until now, by elastic buckling. Fig. 1 represents fabrication process make GAA uniaxially strained from a 100 mm (100) Unibond SOI substrate with 1x10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup>...
The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. is available as free open-source software (FOSS) tool coded Verilog-A. present paper provides short review foundations shows capabilities via characterization modeling based test chip 180 nm CMOS fabricated Europractice.
In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed accumulation regime, as a step, addressing bias-dependency of various key MOSFET parameters (e.g. series resistance, channel width and gate-channel capacitance), non-uniform electron density due corners quantization. A significant bias-dependent resistance variation JL...