A5011010994- Nanowire Synthesis and Applications
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Quantum Structures and Devices
- Semiconductor materials and devices
- Semiconductor materials and interfaces
- GaN-based semiconductor devices and materials
- Quantum Dots Synthesis And Properties
- Photonic and Optical Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Electronic and Structural Properties of Oxides
- Silicon Nanostructures and Photoluminescence
- Ga2O3 and related materials
- solar cell performance optimization
- Molecular Junctions and Nanostructures
- Thin-Film Transistor Technologies
- Semiconductor Lasers and Optical Devices
- Surface and Thin Film Phenomena
- ZnO doping and properties
- Ferroelectric and Piezoelectric Materials
- Concrete Properties and Behavior
- Chalcogenide Semiconductor Thin Films
- Advanced Memory and Neural Computing
- Radio Frequency Integrated Circuit Design
- E-Learning and Knowledge Management
- Urban and spatial planning
Hokkaido University
2014-2024
Japan Science and Technology Agency
2010-2020
Hokkaido University of Science
2008-2019
Judd Systems Technologies (United States)
2013
Gunma University
2005-2006
Toshiba (South Korea)
2005
We report on control of growth directions InAs nanowires Si substrate. achieved to integrate vertical by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Cross-sectional transmission electron microscope and Raman scattering showed that misfit dislocation local strains were accommodated the interface.
We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated Si. threshold current for electroluminescence (EL) was 0.5 mA (current density approximately 0.4 A/cm2), the EL intensity superlinearly increased increasing injections indicating superluminescence behavior. technology...
We report on the formation of core–shell pn junction InP nanowires using a catalyst-free selective-area metalorganic vapor-phase epitaxy (SA-MOVPE) method. A periodically aligned dense nanowire array was fabricated and used in photovoltaic device applications. The exhibited open-circuit voltage (VOC), short-circuit current (ISC) fill factor (FF) levels 0.43 V, 13.72 mA/cm2 0.57, respectively, which indicated solar power conversion efficiency 3.37% under AM1.5G illumination. This study...
III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices platforms. We present position-controlled orientation-controlled growth of InAs, GaAs, InGaAs NWs by selective-area growth, discuss how to control directions NW Si. Basic studies III-V/Si interface showing heteroepitaxial with misfit dislocations coherent without presented. Finally, we demonstrate the integrations a NW-based vertical surrounding-gate field-effect transistor...
We report on selective-area growth of vertically aligned GaAs nanowires Si(111) substrate. Modification the initial surface by pretreatment under an AsH3 atmosphere and low-temperature were important for controlling orientations nanowire surface. also found that size openings strongly affected morphology Si(111). Small diameter reduced antiphase defects improved optical properties in nanowires. Moreover, we realized coherent without misfit dislocation at GaAs/Si interface. Finally,...
In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors InAs NW/Si heterojunction TFET with surrounding-gate architecture high-k dielectrics. Control of resistances in device structure is important for achieving switching. A minimum subthreshold slope (SS) the 21 mV/dec at VDS 0.10 - 1.00 V.
We report on fabrication of tunnel field-effect transistor with III-V nanowire (NW)/Si heterojunction and surrounding-gate structure. The device fabricated by selective-area growth an n+-InAs/undoped-InAs axial NW a p+-Si(111) substrate showed switching behavior average subthreshold slope (SS) 104 mV/dec under reverse bias condition. appeared small supply voltage (Vds=50 mV). Transmission electron microscopy revealed misfit dislocation formed at the interface degraded SS ON-state current....
We study the catalyst-free growth of InP nanowires using selective-area metalorganic vapor phase epitaxy (SA-MOVPE) and show that they undergo transition crystal structures depending on conditions. were grown substrates where mask for template was defined. The only in opening region mask. It found uniform array with hexagonal cross section negligible tapering under two distinctive different conditions to exhibit structures. also orientation size hexagon different, suggesting difference...
Indium phosphide (InP) nanowires, which have crystal phase mixing and transition from zinc blende (ZB) to wurtzite (WZ), are grown in intermediate growth conditions between ZB WZ by using selective-area metalorganic vapor epitaxy (SA-MOVPE). The shape of InP nanowires is tapered unlike or nanowires. A model has been developed for the simply described as relationship angle ratio segments. In addition, peak energy shift photoluminescence measurement was attributed quantum confinement effect...
We report on the fabrication and characterization of vertical InAs nanowire channel field effect transistors (FETs) with high-k/metal gate-all-around structures. Single nanowires were grown Si substrates by selective-area metalorganic vapor phase epitaxy method. The resultant devices exhibited n-channel FET characteristics a threshold voltage around -0.1 V. best device maximum drain current (IDSmax/wG), transconductance (gmmax/wG), on–off ratio (ION/OFF), subthreshold slope (SS) 83 µA/µm,...
We report changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistors by the Zn-pulsed doping technique for InAs nanowire channels. The channel moderately from negative to positive voltage, while keeping a 30 mV/decade under reverse bias direction. formation pseudointrinsic segment is found be important make normally off transistor with subthreshold slope.
We report the experimental demonstration of single-photon and cascaded photon pair emission in infrared, originating from a single InAsP quantum dot embedded standing InP nanowire. A regular array nanowires is fabricated by epitaxial growth on an electron-beam patterned substrate. Photoluminescence spectra taken dots show narrow lines. Superconducting detectors, which have higher sensitivity than avalanche photodiodes enable us to measure auto cross correlations. Clear antibunching observed...
We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization scaling channel lengths. The devices consisted single nanowires with diameter 30 nm grown p-type Si(111) substrates. switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) 0.10 V. Also, pinch-off behavior appeared moderately low VDS, below Reducing length attained subthreshold slope (<60 enhanced drain current, which was 100...
Abstract We report on the recent progress in electronic applications using III–V nanowires (NWs) Si substrates selective-area growth method. This method could align vertical NWs under specific conditions. Detailed studies of NW/Si heterointerface showed possibility achieving coherent regardless misfit dislocations III–V/Si heterojunction. The grown were utilized for high performance field-effect transistors (FETs). Furthermore, heterointerfaces with fewer provided us a unique band...
Abstract Selective-area growth of InGaAs nanowires (NWs) and vertical gate-all-around (VGAA) transistors using the NWs on Silicon-on-insulator (111) substrates were characterized toward future three-dimensional integrated circuit applications III-V NW-based VGAA transistors. On an n-type SOI, transistor acts as a field-effect (FET), involving carrier transport electrostatic modulation inside NW channels. While p-type exhibited tunnel FET properties, at NW/SOI interface. Characterization with...
Crystallographic structure of InAs nanowires, which were grown by selective-area metalorganic vapor phase epitaxy on (111)B-oriented substrates, was investigated transmission electron microscopy (TEM). The TEM images showed that the nanowires had many stacking faults along growth direction. Statistical analysis atomic-layer contained both zincblende and wurtzite crystal phases, whose transition took place in every one to three monolayers. This specific resulted peculiar diffraction patterns....
Semiconductor nanowires (NWs) are good candidate for light-absorbing material in next generation photovoltaic and III–V NW-based multi-heterojunction solar cells using lattice-mismatched system expected as high energy-conversion efficiencies under concentrated light. Here we demonstrate core–shell GaAs NW arrays by catalyst-free selective-area metal organic vapor phase epitaxy (SA-MOVPE) a basis multijunction cells. The reflectance of the array without any anti-reflection coating showed much...
We report surface-passivated core–shell InP nanowire array solar cells fabricated using catalyst-free selective-area metal organic vapor phase epitaxy. Reflectance measurements confirm enhanced light absorption due to significantly reduced reflectance over a wide spectral range. The wide-band-gap outer shell layer of core-multishell nanowires effectively passivates the large surface area nanowires, increasing short-circuit current density and elevating energy conversion efficiency by 6.35%...
III-V compound semiconductor and Ge are promising channel materials for future low-power high-performance integrated circuits. A heterogeneous integration of these on the same platform, however, raises serious problem owing to a huge mismatch carrier mobility. We proposed direct perfectly vertically aligned InAs nanowires as method new alternative circuits demonstrated nanowire-vertical surrounding-gate transistor. Virtually 100% yield was achieved by controlling initial surface high-quality...
Single InGaAs nanowire-top-gate metal–semiconductor field-effect transistors (MESFETs) were fabricated and characterized. Silicon-doped n-InGaAs nanowires (with a typical diameter of 100 nm) grown by catalyst-free selective-area metal–organic vapor-phase epitaxy (SA-MOVPE). The FETs single on SiO2-coated Si substrates defining metal contacts at both ends the top gate between contacts. According to measurements drain current–voltage transfer characteristics, top-gate MESFETs exhibited...
We fabricated InGaAs nanowires (NWs) in SiO 2 mask openings on a GaAs(111)B substrate at growth temperatures of 600–700 °C using catalyst-free selective-area metal organic vapor phase epitaxy. At temperature 600 °C, particle-like depositions occurred, but they decreased number and density when the was increased to 650 disappeared above 675 °C. The heights rates NWs opening diameter from 300 50 nm. Photoluminescence (PL) spectra measured for indicated blue shift peak 0.95 1.3 eV as 700...