A5038123706- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- Speech and Audio Processing
- VLSI and Analog Circuit Testing
- Advanced Adaptive Filtering Techniques
- Interconnection Networks and Systems
- Advanced Image and Video Retrieval Techniques
- CCD and CMOS Imaging Sensors
- Video Coding and Compression Technologies
- Advanced Neural Network Applications
- Advanced Data Compression Techniques
- Blind Source Separation Techniques
- Advanced Vision and Imaging
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Autonomous Vehicle Technology and Safety
- Robotics and Sensor-Based Localization
- Video Surveillance and Tracking Methods
- VLSI and FPGA Design Techniques
- Modular Robots and Swarm Intelligence
- Numerical Methods and Algorithms
Technische Universität Braunschweig
2021-2024
Leibniz University Hannover
2010-2022
Hearing4all
2015-2021
Institut für Mikroelektronik- und Mechatronik-Systeme
2019
Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts data from different sensors, like camera, radar, LiDAR. In ZuSE-KI-AVF project, multiple university, industry partners collaborate to develop a novel massive parallel processor architecture, based on cus-tomized RISC-V host processor, an high-performance vertical vector coprocessor. addition, software development framework is also provided efficiently...
In many applications of machine listening it is useful to know how well an automatic speech recognition system will do before the actual performed. this study we investigate different performance measures with aim predicting word error rates (WERs) in spatial acoustic scenes which type noise, signal-to-noise ratio, parameters for filtering, and amount reverberation are varied. All under consideration based on phoneme posteriorgrams obtained from a deep neural net. While frame-wise entropy...
Numerous approximate adders have been proposed in the literature response to languishing benefits of technology scaling. However, they obtained with an ad-hoc and non-systematic methodology which does not fully exploit design space possibilities. This paper provides a conceptual framework for systematic adders, including hybrid non-equally segmented approaches as well more robust error metrics. The discriminates scenarios, where processing provide significant from those it does; this later...
This paper explores a real- and complex-valued multiply-accumulate (MAC) functional unit for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support are often used to increase the processing performance in modern Compared real-valued SIMD-MAC units, proposed uses same multipliers also butterfly operations. The area overhead complex mode is small. Complex-valued operations speed up algorithms make execution more efficient terms of power consumption. As case...
Bit errors due to radiation effects are becoming increasingly important as the fabrication technologies shrinking with every generation of integrated circuits. The resulting smaller transistors more prone high-energy irradiation. This is relevant in avionics or even automotive, where safety millions cars must be ensured. paper proposes an experiment, multiple FPGAs (Field Programmable Gate Arrays) exposed 2.45MeV neutron irradiation parallel. Bitflips different memory components (Block RAM,...
When using Field-Programmable Gate Arrays (FPGA) in safety-critical and harsh environments, it is important to understand possible faults implement appropriate mitigation prevent critical system errors. Electronic components can be affected by radiation, including naturally occurring background radiation. Due their reconfigurability, FPGAs exhibit not only with regard application data but also the configuration memory, which defines functionality of logic circuit. This paper proposes an...
This paper presents two new architecture optimizations to improve the processing performance of video applications with a high degree data parallelism in VLIW processors. On one hand, register file access mechanism, called X4 operation mode, allows wide operands made up several consecutive registers file, while keeping its normal functionality (i.e. single read/write access). other functional unit is proposed efficiently process typical stereoscopic application based on rank transformation...
Hardware architectures for modern hearing aid devices have to provide ultra low power consumption at a small silicon area and moderate computational performance deal with the continuously growing complexity of signal processing. At same time, they need remain flexible future algorithmic changes. These challenging design goals can be achieved by using Application-Specific Instruction-Set Processors (ASIPs), where baseline architecture is customized target class applications. In this paper,...
Abstract Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need fabricated robust technology nodes order operate reliably. However, these are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In achieve low silicon area costs, power consumption reasonable performance, the processor architecture organization itself is a major influential design...
Research of efficient fault tolerance techniques for digital systems requires insight into the propagation mechanism inside ASIC design. Radiation, high temperature, or charge sharing effects in ultra-deep submicron technologies influence generation and dependent on die location. The proposed methodology links injection to floorplan view a standard cell ASIC. This is achieved by instrumentation gate netlist after place&route, emulation an FPGA system experiment control via interactive user...
The integration of application specific instruction set processors (ASIPs) in hearing aids requires various architectural customizations and software-side optimizations order to meet the stringent power consumption constraints processing performance demands. This paper presents KAVUAKA aid processor its ASIC as a system on chip (SoC). final contains four cores ten co-processors. Each these co-processors were individually customized differ their data path width. are organized two clusters,...
Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore manycore processors can execute a diversity of software applications (e.g, driver assistance systems) written in portable high-level programming languages resulting less porting effort at lower for power-consumption tolerant fields. For instance, the Intel Xeon Phi processor featuring 61 cores...
Abstract On the one hand, processors for hearing aids are highly specialized audio processing, on other hand they have to meet challenging hardware restrictions. This paper aims provide an overview of requirements, architectures, and implementations these processors. Special attention is given increasingly common application-specific instruction-set (ASIPs). The main focus this lies hardware-related aspects such as processor architecture, interfaces, application specific integrated circuit...
Instruction scheduling and register allocation for VLIW architectures are complex problems which computing the optimal solution is often infeasible. Instead, optimization techniques heuristics used to find good solutions in reasonable time. List a well known microcode compaction method, uses weights derived from data dependency graphs of input program its heuristic function. Additional information mechanisms have be order reach better code compaction. In this paper, genetic algorithm tune...
Many complex maneuvers involving aircraft, vehicles and persons are carried out at airport aprons. Manual video surveillance used for safety security purposes is inefficient privacy protection must be guaranteed. In this paper, we propose a system named ASEV that automatically assesses situations surveillance. It combines four main components: low-level image processing unit based on new hardware implementation to extract features in real time, high-level scene analysis, real-time inference...
The development of complex algorithms for advanced driver assistance systems is a challenging task, due to the high innovation rate and processing demands applications in this field. usually supported by software framework that provides an infrastructure (e.g., access sensor data) simulates evaluates algorithms. One problem, especially with computationally intensive algorithms, slow simulation speed. This paper presents prototyping environment connects FPGA-based hardware platform. allows...