A5042519673- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Full-Duplex Wireless Communications
- Energy Harvesting in Wireless Networks
- Cognitive Radio Networks and Spectrum Sensing
- Advancements in Semiconductor Devices and Circuit Design
- Wireless Networks and Protocols
- Interconnection Networks and Systems
- Advanced Neural Network Applications
Taiwan Semiconductor Manufacturing Company (United States)
2025
Columbia University
2022-2024
This article presents a programmable in-memory computing accelerator (PIMCA) for low-precision (1–2 b) deep neural network (DNN) inference. The custom 10T1C bitcell in the (IMC) macro has four additional transistors and one capacitor to perform capacitive-coupling-based multiply accumulation (MAC) analog-mixed-signal (AMS) domain. A containing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256 \times 128$...
Recent SRAM-based in-memory computing (IMC) hardware demonstrates high energy efficiency and throughput for matrix–vector multiplication (MVM), the dominant kernel deep neural networks (DNNs). Earlier IMC macros have employed analog-mixed-signal (AMS) arithmetic hardware. However, those so-called AIMCs suffer from process, voltage, temperature (PVT) variations. Digital (DIMC) macros, on other hand, exhibit better robustness against PVT variations, but they tend to require more silicon area....
This article presents multistep accumulation capacitor coupling static random-access memory (MACC-SRAM), capacitor-based in-memory computing (IMC) SRAM macro for 4-b deep convolutional neural network (DNN) inference. The can simultaneously activate all its 128 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> custom 9T1C bitcells to perform the vector–matrix...
In order to enable the simultaneous transmission and reception of wireless signals on same frequency, a full-duplex (FD) radio must be capable suppressing powerful self-interference (SI) signal emitted from transmitter picked up by receiver. Critically, major bottleneck in wideband FD deployments is need for adaptive SI cancellation (SIC) that would allow system achieve strong across different settings with distinct electromagnetic environments. this work, we evaluate performance an three...
For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the reliability during clock-domain crossing, especially in near-threshold-voltage (NTV) region. Conventional multistage synchronizers reduce probability of but have high latency penalty. This article presents technique titled risk prediction and mitigation (MPAM) that predicts near-future risks by triple-phase clock monitoring circuitry mitigates them metastability-free scheme. Therefore, MPAM enables...
We present a set of experiments utilizing wideband real-time adaptive full-duplex (FD) radios, demonstrating simultaneous transmission and reception on the same frequency channel. Each FD radio consists circulator-based antenna interface, switched-capacitor delay-line-based configurable Radio-Frequency Integrated Circuit (RFIC) that implements Self-Interference Cancellation (SIC), an FPGA optimizes RFIC configuration in under 1.1 sec can adapt to environmental changes 0.3 sec,...
This article presents a timing slack inference and clock frequency adaption technique, named TICA, to mitigate the large pessimistic guardband reserved for process, voltage, temperature (PVT) variations in deeply pipelined ultra-low-voltage (ULV) circuits. TICA can perceive dynamic PVT of circuit with situ cycle borrowing detectors, then infer its runtime slack, adjust accordingly minimize redundant margin timely. Therefore, maintain small amount positive free from costly error correction...