Pattern searches, a key operation in many data analytic applications, often deal with represented by multiple states per dimension. However, hash tables, common software-based pattern search approach, require large amount of additional memory, and thus, are limited the memory wall. A hardware-based solution is to use content-addressable memories (CAMs) that support fast associative searches parallel. Ternary CAMs (TCAMs) bit-wise Hamming distance (HD) based searches. Detecting HD vectors...

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) that are mostly employed as high-performance and high-density prone radiation-induced single-event upsets. Therefore, designing reliable SRAM has always been a serious challenge. In this paper, we propose two novel cells, namely, RHD11 RHD13, provide more attractive features than their latest proposed counterparts....

Field-programmable gate arrays (FPGAs) based on static random access memory (SRAM) are more common than other types, including flash and anti-fuse, because of their infinite configurability high performance. However, following the scaling down CMOS technology, standby power circuits becoming crucial. Logic magnetic RAM (MRAM) can be an attractive replacement for SRAM-based logics thanks to zero leakage compatibilities. Furthermore, in FPGA design, using MRAM instead SRAM results some...

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of most promising candidates for future digital circuits. MTJ-based can offer nonvolatility, endurance, density, low dissipation, and 3-D integration capability with CMOS technology. In recent years, several...

Nearest neighbor (NN) search is an essential operation in many applications, such as one/few-shot learning and image classification. As such, fast low-energy hardware support for accurate NN highly desirable. Ternary content-addressable memories (TCAMs) have been proposed to accelerate few-shot tasks by implementing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> <inf xmlns:xlink="http://www.w3.org/1999/xlink">∞</inf> Hamming distance...

Magnetic random access memory is a promising solution to keep up with the trend of sizing. On other hand, multiple-valued logic has been considered as for some important challenges binary integrated circuits. In this paper, novel ternary magnetic RAM (TMRAM) based on sub-10 nm gate-all-around carbon nanotube transistor (GAA-CNTFET) proposed. The proposed TMRAM cell utilizes tunnel junction (MTJs) provide non-volatility and spin-hall assisted spin-transfer torque method reduce write energy....

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability enduring multiple (SEMUs). Our simulation results show that, our HRUT higher robustness against SEMUs as compared with other recently radiation hardened latches. We also explored effects process temperature variations on different design parameters such delay power consumption leading SEU...

Very large-scale integrated circuit design, based on today's CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply cause new concerns such as high leakage current, increase radiation sensitivity. As a solution for design challenges, hybrid MTJ/CMOS can resolve the issue of bring advantage nonvolatility. However, radiation-induced soft error is still an designs they need peripheral components. result, these...

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features overcome aforesaid of CMOS technology. The hybrid MTJ/CMOS circuits offer low consumption, nonvolatility, performance. This paper proposes two novel approximate full-adder (AXMA)...

In this article, four novel approximate full-adder (AXFA) circuits based on the emerging magnetic tunnel junction (MTJ) device is proposed. The proposed FAs (MFAs) offer full nonvolatility, low area, and considerably lower energy consumption than their previous counterparts. Also, two of MFAs have advantage single event upset (SEU) tolerance. Simulation results reveal that designs over 50% efficiency in comparison with considered fully nonvolatile MFAs. Using adders design an Gaussian...

Associative memories (AMs), which efficiently "associate" input queries with appropriate data words/locations in the memory, are powerful in-memory-computing cores. Harnessing benefits of AMs requires cross-layer design efforts that span from devices and circuits to architectures applications. This paper showcases representative AM designs based on different non-volatile memory technologies (resistive RAM (RRAM), ferroelectric FETs (FeFETs), Flash). End-to-end evaluations for machine...

Magnetoresistive memories, such as spin-transfer torque random access memory and magnetic latches (M-latch), are emerging technologies that offer attractive features, high density, low leakage, nonvolatility compared with conventional static memory. In this paper, we have proposed two single-event upset tolerant M-latch circuits in which their CMOS peripheral robust against radiation effects. Similar to the circuit, our M-latches employ tunnel junction elements. Therefore, they consume...

Reduction of leakage power and vulnerability to radiation are critical challenges in modern nanometer CMOS technologies because scaling down requirement. Spintronic logic has been progressed realize these demands based on magnetic-based elements properties especially magnetic tunnel junction (MTJ) such as radiation-hardened, non-volatility, process compatibility. A novel soft-error tolerant highly reliable latch circuit is proposed this paper which a promising choice for low-power...

Generation of random numbers is one the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are attractive features offered by Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design true number generation using MTJs proposed. Our proposed offers speed, power truly generation. our design, we employed two...

Content-addressable memories (CAMs) are widely used for data-centric applications where one must search data patterns. CMOS CAMs can incur large areas and, hence, power consumption. Nonvolatile (NV) devices, such as ferroelectric field-effect transistors (FeFETs) and resistive random access memories, have been in the design of NV to improve both logic density To further density, this article proposes a compact, multistate CAM (MCAM) that store 3 bits cell using just FeFET three FinFETs per...

Approximate computing (AC) is a recently emerged paradigm that can trade in accuracy for power, area, and delay accuracy-insensitive applications, such as image processing. Magnetic tunnel junction (MTJ) cells further these AC advancements result of their near-zero current leakage. In addition, due to the non-volatility MTJs, an MTJ-based circuit switch into completely OFF state during idle cycles power savings without loss data or need extra components. this article, two novel approximate...

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed evaluated. The radiation hardened cells capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree robustness against multiple (SEMUs). Over previous RATF2 offer lower area power overhead. Hspice simulation results through comparison with some prominent state-of-the-art that our robust have smaller overhead (RAFT1 offers 58% than DICE), delay product (RATF1 231.33%...

As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today’s logic circuits. Emerging spin-based circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show great potential overcome the aforementioned issues. However, are still MTJ-based as they need sequential peripheral for sensing MTJs. This paper proposes novel low-cost...

Downscaling trend in CMOS technology on the one hand and reducing supply voltage of circuits other hand, make devices more susceptive to soft errors such as SEU. Latch are prone be affected by SEUs. In this article, we propose a new circuit design latch using redundancy with aim immunity against According simulation results, our not only guaranties full immunity, but also has advantage occupying less area consuming much power performance penalty comparison SEU immune latches. The results...

This paper proposes a new magnetic random access memory (MRAM)-backed SRAM (MSRAM) cell to be used in structure of programmable logic devices such as field gate array (FPGA). The proposed contains fast part and also backup MRAM part. An FPGA based on the MSRAM will offer good performance, very low power consumption, nonvolatility. Besides, by increasing number parts, it can capability multiple design implementations. Furthermore, facilitating gating tolerance radiation-induced soft errors...

Following the scale down of complementary metal-oxide semiconductor (CMOS) technology, radiation-induced soft errors have become a concerning issue in CMOS circuit design. Today's integrated circuits suffer from single event double node upset (SEDU) that takes place when an energetic particle strike affects two adjacent nodes. In this letter, magnetic random access memory block capable tolerating SEDUs is proposed and evaluated. The utilizes hybrid design CMOS-based technology considerably...

True random number generators (TRNGs) are critical in cryptography and security systems. This paper presents a reliable TRNG relying on the stochastic switching of spin-transfer torque magnetic tunnel junction (STT-MTJ) sub-critical current regime. Using an XOR-based structure our proposed design eliminates need for succeeding post-processing units while ensuring generation numbers, even presence major variations. Moreover, utilizing gate-all-around (GAA) carbon nanotube field-effect...

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step a tolerant ASIC design. In order to have cost effective protection against radiation effects combinational logics, fast method for identification most susceptive gates paths needed. this paper, efficient, propagation probability (SEPP) presented its performance evaluated. This takes into account all three masking factors multi cycles. It also considers multiple event transients as new challenge circuit...