In this paper, we present a two-phase framework that integrates task assignment, ordering and voltage selection (VS) together to minimize energy consumption of real-time dependent tasks executing on given number variable processors. Task assignment in the first phase strive maximize opportunities can be exploited for lowering levels during second phase, i.e., selection. formulate VS problem as an Integer Programming (IP) solve IP efficiently. Experimental results demonstrate our is very...

Energy consumption has become an increasingly important consideration in designing many real-time embedded systems. Variable voltage processors, if used properly, can dramatically reduce such system energy consumption. In this paper, we present a technique to determine settings for variable processor that utilizes fixed priority assignment schedule jobs. Our approach also produces the minimum constant needed feasibly entire job set. algorithms lead significant saving compared with previously...

We report local control of nanomagnets that can be arranged to perform computation in a cellular automata-like architecture. This letter represents the first demonstration deterministically placed quantum-dot automata (QCA) devices (of any implementation), where are controlled by on-chip fields.

Thermal effects in MPSoCs may cause the violation of timing constraints real-time systems. This paper presents a mixed integer linear programming based solution to this problem. Tasks are assigned and scheduled an MPSoC minimize peak temperature, subject constraints. The proposed approach outperforms existing methods, reducing temperature by up 24.66°C average 8.75°C when compared minimal-energy solutions. We also present heuristic for use on large problem instances. Steady-state thermal...

Multiprocessor system-on-chip (MPSoC) has been widely used in many real-time embedded systems where both soft-error reliability (SER) and lifetime (LTR) are key concerns. Many existing works have investigated them, but they focus either on handling one of the two concerns or improving type under constraint other. These techniques thus not applicable to maximize SER LTR simultaneously, which is highly desired some real-world applications. In this paper, we study joint optimization for MPSoCs....

Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor system-on-chip (MPSoC) use in hard real-time systems. This paper formalizes the temperature-aware MPSoC assignment scheduling problem presents an optimal phased steady-state mixed integer linear programming-based solution that considers impact of decisions on thermal profiles to directly minimize chip peak temperature. We also introduce a flexible heuristic framework for task permits system...

With the continuous scaling of CMOS devices, increase in power density and system integration level have not only resulted huge energy consumption but also led to elevated chip temperature. Thus, efficient task scheduling with thermal consideration has become a pressing research issue computing systems, especially for real-time embedded systems limited cooling techniques. In this paper, we design two-stage energy-efficient temperature-aware scheme heterogeneous multiprocessor system-on-chip...

Dense analog synaptic crossbar arrays are a promising candidate for neuromorphic hardware accelerators due to the ability mitigate data movement by performing in-situ vector-matrix products and weight updates within storage array itself. However, many cells suffer from long latencies or low dynamic ranges, limiting achievable performance. In this work, we demonstrate that voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFET) can be...

Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of TFETs that affect analog circuit design are studied. To demonstrate how can enhance performance or change topology circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits examined. It shown promising low-power low-voltage designs, wherein transistors biased at low-to-moderate densities. Comparing 14-nm III-V...

CMOS scaling has greatly increased concerns for both lifetime reliability due to permanent faults and soft-error transient faults. Most existing works only focus on one of the two concerns, but often times techniques used increase type may adversely impact other type. A few efforts do consider types together use different metrics quantify reliability. However, many systems, user's concern is maximize system availability by improving mean time failure (MTTF), regardless whether caused or...

Ternary content addressable memories (TCAMs) represent a form of logic-in-memory and are currently widely used in routers, caches, efficient machine learning models. From technology prospective, researchers have begun to consider various non-volatile (NV) memory technologies design NV TCAMs that may offer improvements with respect figures merit, such as energy delay when compared conventional CMOS designs. Among these devices, ferroelectric field effect transistors (FeFETs) stand out due...

With pervasive applications of medical imaging in health-care, biomedical image segmentation plays a central role quantitative analysis, clinical diagnosis, and intervention. Since manual annotation suffers limited reproducibility, arduous efforts, excessive time, automatic is desired to process increasingly larger scale histopathological data. Recently, deep neural networks (DNNs), particularly fully convolutional (FCNs), have been widely applied segmentation, attaining much improved...

Abstract Deep learning (DL) is a powerful tool for mining features from data, which can theoretically avoid assumptions (e.g., linear events) constraining conventional interpolation methods. Motivated by this and inspired image-to-image translation, we applied DL to irregularly regularly missing data reconstruction with the aim of transforming incomplete into corresponding complete data. To accomplish this, established model architecture randomly sampled as input output, was based on an...

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other non-volatile memories (NVMs). Content Addressable Memories (CAMs) a form of IMC that performs parallel searches matched entries memory array given input query. CAMs widely used data-centric applications involve pattern matching and search functionality. To accommodate ever expanding data, it is attractive to resort analog CAM density improvement....

Among the beyond-complementary metal-oxide- semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of most promising. FeFETs studied by all major manufacturers, and experimentally, making rapid progress. also stand out with unique hysteretic Ids-Vgs characteristic that allows a device to function both switch nonvolatile (NV) storage element. We exploit this FeFET property build two categories fine-grained logic-in-memory (LiM)...

Data transfer between a processor and memory frequently represents bottleneck with respect to improving application-level performance. Computing in (CiM), where logic arithmetic operations are performed memory, could significantly reduce both energy consumption computational overheads associated data transfer. Compact, low-power, fast CiM designs ultimately lead improved This paper introduces architecture based on ferroelectric field effect transistors (FeFETs). The design can serve as...

Co-exploration of neural architectures and hardware design is promising due to its capability simultaneously optimize network accuracy efficiency. However, state-of-the-art architecture search algorithms for the co-exploration are dedicated conventional von-Neumann computing architecture, whose performance heavily limited by well-known memory wall. In this article, we first bring computing-in-memory which can easily transcend wall, interplay with search, aiming find most efficient high...

Pattern searches, a key operation in many data analytic applications, often deal with represented by multiple states per dimension. However, hash tables, common software-based pattern search approach, require large amount of additional memory, and thus, are limited the memory wall. A hardware-based solution is to use content-addressable memories (CAMs) that support fast associative searches parallel. Ternary CAMs (TCAMs) bit-wise Hamming distance (HD) based searches. Detecting HD vectors...

In this paper, we present a two-phase framework that integrates task assignment, ordering and voltage selection (VS) together to minimize energy consumption of real-time dependent tasks executing on given number variable processors. Task assignment in the first phase strive maximize opportunities can be exploited for lowering levels during second phase, i.e., selection. formulate VS problem as an Integer Programming (IP) solve IP efficiently. Experimental results demonstrate our is very...