A5102839569- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and interfaces
- Advanced Thermoelectric Materials and Devices
- Thermal properties of materials
- Nanowire Synthesis and Applications
- Silicon Nanostructures and Photoluminescence
- Integrated Circuits and Semiconductor Failure Analysis
- Thin-Film Transistor Technologies
- Thermal Radiation and Cooling Technologies
- Silicon and Solar Cell Technologies
- Analytical Chemistry and Sensors
- Advanced Memory and Neural Computing
- Quantum and electron transport phenomena
- Microfluidic and Bio-sensing Technologies
- 3D Printing in Biomedical Research
- Surface and Thin Film Phenomena
- Molecular Junctions and Nanostructures
- Metal and Thin Film Mechanics
- Semiconductor Quantum Structures and Devices
- Ammonia Synthesis and Nitrogen Reduction
- Hydrogen Storage and Materials
- Silicon Carbide Semiconductor Technologies
- Advanced MEMS and NEMS Technologies
- Neuroscience and Neural Engineering
Sungkyunkwan University
2024-2025
Hallym University
2015-2023
Electronics and Telecommunications Research Institute
2004-2013
University of Waterloo
2009-2011
Korea Advanced Institute of Science and Technology
2010
Advanced Institute of Convergence Technology
2009
Kwangwoon University
2008
Korea Institute of Science & Technology Information
2005
Reduced graphene oxide (rGO) has wide application as a nanofiller in the fabrication of electroconductive biocomposites due to its exceptional properties. However, hydrophobicity and chemical stability rGO limit ability be incorporated into precursor polymers for physical mixing during biocomposite fabrication. Moreover, until now, no suitable rGO-combining biomaterials that are stable, soluble, biocompatible, 3D printable have been developed. In this study, we fabricated digital light...
The theoretical and experimental current–voltage characteristics of 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) are discussed. manufactured SB-MOSFET shows large on/off current ratio with low leakage less than 10−4 μA/μm. saturation is 120 μA/μm when drain gate voltage 1 3 V, respectively. fitted using newly developed model. From the analysis, off- on-current mainly attributed to thermionic tunneling current,...
Atomic layer deposition (ALD) of high-k dielectric films on MoS2 channels can lead to inadvertent remote electron doping owing nonequilibrium ALD conditions, such as the low temperatures and short purge times required for pinhole-free coating, well weak physical adsorption precursors MoS2. In this study, we propose application a simple effective H2O vapor post-treatment (H2O PT) at 100 °C immediately after complete integration bottom- top-gate monolayer field-effect transistors (FETs),...
Trap density, lifetime, and the Schottky barrier height of erbium-silicided diode are evaluated using equivalent circuit method. The extracted trap for hole determined as 1.5/spl times/10/sup 13/ traps/cm/sup 2/, 3.75 ms 0.76 eV, respectively. By developed method, interface can be quantitatively.
Using a Green’s function method based on an elastic wave equation, the effects of surface roughness and nanowire-contact interface scattering phonon thermal conductivity are studied at low temperatures. It is found that geometry between nanowire its contacts affects transmission small energies related to gapless modes it gives rise deviated results from universal conductance. also shown crucial in suppression with reducing size by averaging over rough-surface configurations. Furthermore,...
This paper experimentally investigates the unique behavior of transconductance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> ) in Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When height (SBH) or a scaling parameter is not properly optimized, peculiar shape observed. Thus, can be used as novel metric that exhibits transition carrier injection mechanisms from thermionic...
We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated silicon-on-insulator (SOI) structure by pattern-dependent oxidation (PADOX) technique, combined e-beam lithography. Drain conductances measured at 4.2 K approach large values the order microsiemens, exhibiting Coulomb oscillations...
The current–voltage characteristics of erbium-silicided n-type Schottky barrier tunnel transistors (SBTTs) are discussed. SBTTs with 60 nm gate lengths shows typical transistor behaviors in drain current to voltage characteristics. on/off ratio is about 105 at low regime However, the tends decrease as increases. From numerical simulation results, increase off-current mainly attributed thermionic and tunneling current, respectively. This phenomenon explained by using induced thickness thinning effect.
We analyze the performance of a telecommunications management network (TMN) system using models networks queues, Jackson's theorem, and simulation. TMN systems for managing public asynchronous transfer mode (ATM) generally have four-level hierarchical structure consisting system, few element (EMSs), several pairs agents ATM switches. construct queuing present formulae to calculate its measures: distributions queue lengths waiting times, mean message response time, maximum throughput. perform...
Schottky-barrier (SB) heights of erbium and platinum silicides are evaluated using current–voltage capacitance–voltage methods in the Schottky diodes. For erbium-silicided diodes, extracted SB show big differences depending on extraction methods, due to existence interface traps. The traps silicide efficiently cured by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hboxN_2$</tex> annealing. Various sizes erbium/platinum-silicided n/p-type...
The current–voltage characteristics of a Schottky barrier tunnel transistor (SBTT) are simulated by considering the internal voltage drop at and using current continuity condition between tunneling channel current. numerical results show typical behaviors as can be found in many experimental results. From these results, significantly higher threshold is expected for SBTT compared to conventional metal–oxide–semiconductor field-effect transistors, because suppression low gate voltage. For...
A dopant-segregated (DS) Schottky-barrier (DSSB) FinFET SONOS for NAND flash memory with a proposed architecture is demonstrated the first time. DSSB technique nickel-silicided source/drain (S/D) integrated in 30-50-nm range of fin width. Compared conventional SONOS, boasts very fast programming time low voltage. For state, hot electrons triggered by sharp band bending at DS S/D region are used. As result, threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D logic devices and flash memory. To apply DSSB to memory, a novel spacer-free structure successfully implemented. The shows good distribution programmed V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> by one-time programming with high-speed (a shift 2.9 @ 32 ns) due use unique local injection carriers from S/D junctions it not affected...
A novel dopant segregated Schottky barrier (DSSB) FinFET SONOS device is demonstrated in terms of multi functioning a high speed NAND-type flash memory and capacitorless 1T-DRAM. In addition, program mechanism that uses energy band engineered hot electrons (EBEHE) energized by sharp bending at the edge source/drain (S/D) proposed for programming operation. short time 100 ns low voltage 12 V yield <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg extracted with the variation width. Using this structure, Seebeck coefficients measured. obtained maximum coefficient values 122 μV/K for p-leg and -94 n-leg. attainable power factor is 0.74 mW/m K(2) at room temperature.
Silicon-based thermoelectric nanowires were fabricated by using complementary metal–oxide–semiconductor (CMOS) technology. 50 nm width n- and p-type silicon (SiNWs) manufactured a conventional photolithography method on 8 inch wafer. For the evaluation of Seebeck coefficients nanowires, heater temperature sensor embedded test patterns fabricated. Moreover, for elimination electrical thermal contact resistance issues, SiNWs, sensors monolithically CMOS process. validation measurement an...
The authors investigate the electrical and structural properties of high-k Er-silicate film formed by interfacial reaction between Er SiO2 films. increase in rapid thermal annealing temperature leads to reduction interface trap density one order magnitude, indicating improvement quality gate dielectric. increased capacitance value dielectric with treatment is attributed part thickness relative constant caused chemical bonding change from Si-rich Er-rich silicate.