Efficient handling of faults during operation is highly dependent on the interval (latency) from time embedded instruments detect errors to when fault manager localizes errors. In this paper, we propose a self-reconfiguring IEEE 1687 network in which all that have detected are automatically included scan path. To enable self-reconfiguration, modified segment insertion bit (SIB) compliant 1687. We provide analyses error detection and localization for single multiple faults, suggest how should...

As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on injection and handling. Our consists of (1) model with set components (devices) each equipped detection features, so called instruments, (2) Instrument Access Infrastructure (IAI) based IEEE P1687 connects the (3) Fault Indication Propagation (FIPI) propagates indications to system-level, (4) Resource Manager (RM) schedule jobs statuses,...

Efficient handling of faults during operation is highly dependent on the interval (latency) from time embedded monitoring instruments detect to when fault manager localizes faults. In this article, we propose a self-reconfiguring IEEE 1687 network in which all that have detected are automatically included scan path, and detection localization module hardware detects configuration after self-reconfiguration extracts error codes reported by instruments. To enable self-reconfiguration, modified...

The probability for errors to occur in electronic systems is not known advance, but depends on many factors including influence from the environment where system operates. In this paper, it demonstrated that inaccurate estimates of error lead loss performance a well fault tolerance technique, Roll-back Recovery with checkpointing (RRC). To regain lost performance, method estimating along an adjustment technique are proposed. Using simulator tool has been developed enable experimentation,...

This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked (SICs) by planning, under power constraint. Test planning involves co-optimization associated with time hardware. architecture is considered compliant IEEE 1149.1 standard. A model presented calculating the any plan a given IC SIC. An algorithm proposed minimizing cost. Experiments are performed several ITC'02 benchmark to compare efficiency constrained against near optimal results...

Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases completion (execution) time. For non-real-time systems, research have focused on optimizing and shown it is possible to find optimal number checkpoints average execution minimal. While minimal important, real-time systems important provide a high...

Integrated circuits (ICs) with a single chip (die) are typically tested test flow consisting of two instances: (1) wafer sort for the bare and (2) package packaged IC. For ICs stacked chips - 3D Stacked there many possible instances, even more flows, no commonly used flow. In this paper, we propose selection algorithm (TFSA) to obtain given The TFSA results in IC, such that expected total time produce each good is minimized. We implemented TFSA, three straightforward schemes an exhaustive...

Efficient handling of faults during operation is highly dependent on the interval (latency) from time embedded instruments detect errors to when fault manager localizes errors. Detection and localization latencies are network connecting fault-monitoring manager. The can be dedicated data, or used for functional as well-posing a trade-off between cost performance (or predictability). As middle-ground solution, networks based existing IEEE 1687 have been proposed. In this paper, we provide an...

Correct operation of real-time systems (RTS) is defined as producing correct results within given time constraints (deadlines). As RTS are becoming more susceptible to soft errors, employing fault-tolerant techniques crucial. Roll-back Recovery with Checkpointing (RRC) an efficient technique. However, RRC introduces a overhead which depends on the number checkpoints. The imposed may cause deadline violations. Therefore, it important at design have metric evaluate what extent constraint met...

Employing fault tolerance often introduces a time overhead, which may cause deadline violation in real-time systems (RTS). Therefore, for RTS it is important to optimize the techniques such that probability meet deadlines, i.e. Level of Confidence (LoC), maximized. Previous studies have focused on evaluating LoC equidistant checkpointing. However, no addressed problem non-equidistant In this work, we provide an expression evaluate checkpointing, and propose Clustered Checkpointing method...