Graph convolutional neural networks (GCNs) have emerged as an effective approach to extend deep learning for graph data analytics. Given that graphs are usually irregular, nodes in a may varying number of neighbors, processing GCNs efficiently pose significant challenge on the underlying hardware. Although specialized GCN accelerators been proposed deliver better performance over generic processors, prior not only under-utilize compute engine, but also impose redundant accesses reduce...

Network-on-Chips (NoCs) are the de facto choice for designing interconnect fabric in multicore chips due to their regularity, efficiency, simplicity, and scalability. However, NoC suffers from excessive static power dynamic energy transistor leakage current data movement between cores caches. Power consumption issues only exacerbated by ever decreasing technology sizes. Dynamic Voltage Frequency Scaling (DVFS) is one technique that seeks reduce energy; however this often occurs at expense of...

The design space for energy-efficient Network-on-Chips (NoCs) has expanded significantly comprising a number of techniques. simultaneous application these techniques to yield maximum energy efficiency requires the monitoring large system parameters which often results in substantial engineering efforts and complicated control policies. This motivates us explore use reinforcement learning (RL) approach that automatically learns an optimal policy improve NoC efficiency. First, we deploy...

Machine learning (ML) architectures such as Deep Neural Networks (DNNs) have achieved unprecedented accuracy on modern applications image classification and speech recognition. With power dissipation becoming a major concern in ML architectures, computer architects focused designing both energy-efficient hardware platforms well optimizing algorithms. To dramatically reduce consumption increase parallelism neural network accelerators, disruptive technology silicon photonics has been proposed...

The increased computational capability in heterogeneous manycore architectures facilitates the concurrent execution of many applications. This requires, among other things, a flexible, high-performance, and energy-efficient communication fabric capable handling variety traffic patterns needed for running multiple applications at same time. Such stringent requirements are posing major challenge current Network-on-Chips (NoCs) design. In this paper, we propose Adapt-NoC, flexible NoC...

The modified-signed-digit (MSD) number system offers parallel addition and subtraction of any two numbers, with carry propagation constrained only between adjacent digits. Based on MSD addition, algorithms for multiplication division are developed in this paper. optical implementations these arithmetic the basis symbolic substitution (SS). space-invariant nature SS matches well presented. potential advantages using computing include significant increase speed, full exploitation parallelism,...

Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as flexible and scalable solution to the increasing wire delay constraints in deep sub-micron regime. However, shrinking feature size limits performance NoCs due power area constraints. Research into optimization has shown that reduction buffers NoC routers reduces overhead but degrades network performance. In this paper, we propose iDEAL, low-power area-efficient architecture reducing within...

As power dissipation in future Networks-on-Chips (NoCs) is projected to be a major bottleneck, researchers are actively engaged developing alternate power-efficient technology solutions. Photonic interconnects disruptive solution that capable of delivering the communication bandwidth at low when number cores scaled large numbers. Similarly, 3D stacking another interconnect can lead energy/bit for communication. In this paper, we propose combine photonic with develop scalable, reconfigurable,...

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for growing number of cores on chip. While NoCs can deliver sufficient bandwidth and enhance scalability, suffer from high power consumption due to router microarchitecture channels that facilitate inter-core communication. As technology keeps scaling down in nanometer regime, unpredictable device behavior aging, infant mortality, design defects, soft errors, aggressive design, process-voltage-temperature...

Network-on-Chips (NoCs) are becoming the standard communication fabric for multi-core and system on a chip (SoC) architectures. As technology continues to scale, transistors wires increasingly vulnerable various fault mechanisms, especially timing errors, resulting in exacerbation of energy efficiency performance NoCs. Typical techniques handling errors reactive nature, responding faults after their occurrence. They rely error detection/correction which have resulted excessive power...

With the end of Dennard scaling, highly-parallel and specialized hardware accelerators have been proposed to improve throughput energy-efficiency deep neural network (DNN) models for various applications. However, collective data movement primitives such as multicast broadcast that are required multiply-and-accumulate (MAC) computation in DNN expensive, require excessive energy latency when implemented with electrical networks. This consequently limits scalability performance electronic...

A new interconnection network for massively parallel computing is introduced. This called an optical multi-mesh hypercube (OMMH) network. The OMMH integrates positive features of both (small diameter, high connectivity, symmetry, simple control and routing, fault tolerance, etc.) mesh (constant node degree scalability) topologies at the same time circumvents their limitations (e.g., lack scalability hypercubes, large diameter meshes). can maintain a constant regardless increase in size. In...

Multi-core chips or chip multiprocessors (CMPs) are becoming the de facto architecture for scaling up performance and taking advantage of increasing transistor count on within reasonable power consumption levels. The projected increase in number cores future CMPs is putting stringent demands design on-chip network (or network-on-chip, NOC). Nanophotonic interconnects have recently emerged as a viable alternate technology solution NOC because their higher communication bandwidth, much reduced...

Optical interconnects are becoming ubiquitous for short-range communication within boards and racks due to higher bandwidth at lower power dissipation when compared metallic interconnects. Efficient multiplexing techniques (wavelengths, time, space) allow bandwidths scale; static or predetermined resource allocation of wavelengths can be detrimental network performance nonuniform (adversial) workloads. Dynamic reallocation (DBR) based on actual traffic pattern lead improved by utilizing idle...

We propose a novel antenna design enabled by 3-D printing technology for future wireless intra-chip interconnects aiming at applications of multicore architectures and system-on-chips (SoCs).In our proposed we use vertical quarter-wavelength monopoles 160 GHz on ground plane to avoid low radiation efficiency caused the silicon substrate.The are surrounded specially-designed dielectric property distribution.This additional degree freedom in is used tailor electromagnetic wave propagation.As...

Current multi-/many-core systems spend large amounts of time and power transmitting data across on-chip interconnects. This problem is aggravated when data-intensive applications, such as machine learning pattern recognition, are executed in these systems. Recent studies show that some applications can tolerate modest errors, thus opening a new design dimension, namely, trading result quality for better system performance. In this article, we explore application error tolerance propose an...

Deep Neural Network (DNN) applications are pervasive. However as demands for these continue to increase, so is the challenges designing flexible and scalable architectures multi-application implementation. Such accelerators require innovative architecture with Network-on-Chips (NoCs), parallelism exploitation, better on-chip memory organization adequately support diverse computation, memory, communication needs. In this paper, we propose Venus, a versatile DNN accelerator design that can...

The relevance of introducing optical interconnects (OI's) in monoprocessors and multiprocessors is studied from an architectural point view. We show that perhaps the major explanation for why technologies have nearly been unable to penetrate into computers OI's generally do not shorten memory-access time, which most critical issue today's stored-program machines. In time dominated by electronic latency memory itself. Thus implementing inside hierarchy without changing architecture cannot...

As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs future multicore many-core architectures. Two disruptive on the horizon nanophotonic interconnects (NIs) 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing reasonable performance-per-watt future. Three-dimensional stacking reduce interconnect distance increase...

The increasing number of cores on a chip has made the network (NoC) concept standard communication paradigm for multiprocessors. A fault in an NoC leads to undesirable ramifications that can severely impact performance chip. Therefore, it is vital design tolerant NoCs. In this paper, we present Shield , reliable router architecture unique ability tolerate both hard and soft errors routing pipeline using techniques such as spatial redundancy, exploitation idle cycles, bypassing faulty...

As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these is proving to be difficult due the explosion of design space complexity handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC framework which introduces architectural innovations uses reinforcement learning...

Heterogeneous manycore architectures are deployed to simultaneously run multiple and diverse applications. This requires various computing capabilities (CPUs, GPUs, accelerators), an efficient network-on-chip (NoC) architecture concurrently handle application communication behavior. However, supporting the concurrent requirements of applications is challenging due dynamic mapping, complexity handling distinct patterns limited on-chip resources. In this paper, we propose Adapt-NoC, a...

We propose CURE, a deep reinforcement learning (DRL)-based NoC design framework that simultaneously reduces network latency, improves energy-efficiency, and tolerates transient errors permanent faults. CURE has several architectural innovations DRL-based hardware controller to manage complexity optimize trade-offs. First, in we reversible multi-function adaptive channels (RMCs) reduce power consumption latency. Second, implement new fault-secure error correction each router enhance...

In pursuit of higher inference accuracy, deep neural network (DNN) models have significantly increased in complexity and size. To overcome the consequent computational challenges, scalable chiplet-based accelerators been proposed. However, data communication using metallic-based interconnects these DNN is becoming a primary obstacle to performance, energy efficiency, scalability. The photonic can provide adequate support due some superior properties like low latency, high bandwidth ease...