Libo Chang

ORCID: 0000-0003-4778-3295
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About
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Research Areas
  • CCD and CMOS Imaging Sensors
  • Advanced Neural Network Applications
  • Advanced Image and Video Retrieval Techniques
  • Underwater Vehicles and Communication Systems
  • Advanced Memory and Neural Computing
  • Seismic Imaging and Inversion Techniques
  • Synthetic Aperture Radar (SAR) Applications and Techniques
  • Robotics and Sensor-Based Localization
  • Ginseng Biological Effects and Applications
  • Robotic Path Planning Algorithms
  • Neural Networks and Applications
  • Phytochemistry and biological activity of medicinal plants
  • Distributed and Parallel Computing Systems
  • Interconnection Networks and Systems
  • Brain Tumor Detection and Classification
  • Infrared Target Detection Methodologies
  • Chromatography in Natural Products
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Domain Adaptation and Few-Shot Learning
  • Advanced Vision and Imaging
  • Engineering and Test Systems
  • Underwater Acoustics Research
  • Advanced SAR Imaging Techniques
  • Embedded Systems and FPGA Design
  • Digital Image Processing Techniques

Northwestern Polytechnical University
2019-2023

Xi’an University of Posts and Telecommunications
2013-2022

Northwest Normal University
2021

Northwest A&F University
2018

Renmin University of China
2018

The expansion and improvement of synthetic aperture radar (SAR) technology have greatly enhanced its practicality. SAR imaging requires real-time processing with limited power consumption for large input images. Designing a specific heterogeneous array processor is an effective approach to meet the constraints requirements application system. In this paper, taking commonly used algorithm imaging-the chirp scaling (CSA)-as example, characteristics each calculation stage in process analyzed,...

10.3390/s19153409 article EN cc-by Sensors 2019-08-03

In order to improve the computational efficiency of convolutional neural networks (CNNs) for object detection on reconfigurable platforms such as field-programmable gate arrays (FPGAs), we propose a CNN processor with hierarchical pipelining and multicore computing based parallel parameter constraints. First, pipelined processing architecture that can adapt computations on-chip memory requirements different layers. We present design configure units while adjusting interconnection utilization...

10.1109/tvlsi.2021.3109580 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2021-09-13

The satellite-borne SAR image intelligent processing system needs to process on-orbit real-time imaging and various tasks of applications, for which reason designing a dedicated high-efficient single-chip multi-processor is prioritized necessity that can simultaneously satisfy requirements low power consumption. Aiming at on-chip data organization memory access structure, two typical models SAR(synthetic aperture radar) CSA (chirp scaling) neural network VGG-11 are analyzed, then...

10.1051/jnwpu/20213930510 article EN cc-by Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 2021-06-01

Mixed-precision quantization can compress the size of Convolution Neural Networks (CNNs) without reducing accuracy network. A fixed bit width CNN accelerator needs to match largest in mixed- precision CNNs, which cause a huge waste resource. In order multiple we propose reconfigurable microprocessing element (RmPE) that supports multi-precision parallel multiplication and addition operations. After testing, when with RmPE infers mixed-precision VGG-16 ResNet-50 on Ultra96-V2 platform,...

10.1109/icmtma54903.2022.00008 article EN 2022 14th International Conference on Measuring Technology and Mechatronics Automation (ICMTMA) 2022-01-01

As the latest generation of digital video coding standard, HEVC has technically optimized multiple modules such as related frame prediction, block processing and entropy in frequency decoding framework. However, flexible efficient algorithms make amount calculation reconstruction process increase dramatically. The energy efficiency traditional processors is limited, difficult to meet current needs ultra-high-definition playback. For most important time-consuming bitstream analysis part...

10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00157 article EN 2021-09-01

10.1109/estc.2012.6485905 article EN 2012 4th Electronic System-Integration Technology Conference 2012-09-01

To solve the problem of low computing efficiency existing accelerators for convolutional neural network (CNNs), which caused by inability to adapt characteristics mode and caching mixed-precision quantized CNNs model, we propose a reconfigurable CNN processor in this paper, consists adaptable unit, flexible on-chip cache unit macro-instruction set. The multi-core can be reconstructed according structure models constraints resources, improve utilization resources. elastic buffer data access...

10.1051/jnwpu/20224020344 article EN cc-by Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 2022-04-01

<p indent=0mm>Quantization is the main method to compress convolutional neural networks and accelerate network inference. Most existing quantization methods quantize all layers same bit width. Mixed-precision can obtain higher precision under compression ratio, but it difficult find a mixed-precision strategy. To solve this problem, mixed-clipping based on reinforcement learning proposed. It uses search for strategy, clip weight data according searched strategy before quantization. This...

10.3724/sp.j.1089.2021.18509 article EN Journal of Computer-Aided Design & Computer Graphics 2021-04-01

We propose a hardware/software co-design framework, which leverages hardware-aware quantization and reconfigurable processor to improve the computational efficiency of convolutional neural networks (CNNs) on tiny IoT devices based platforms. Firstly, we proposed multi-objective optimization value function that can weigh accuracy, size CNN models, delay, mixed- precision algorithm deep reinforcement learning. Secondly, adapt computing characteristics various quantized as well array an on-chip...

10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00033 article EN 2021-09-01
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