A5062634345- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- GaN-based semiconductor devices and materials
- Ferroelectric and Negative Capacitance Devices
- Foot and Ankle Surgery
- Radio Frequency Integrated Circuit Design
- Ga2O3 and related materials
- Silicon Carbide Semiconductor Technologies
- Sports injuries and prevention
- ZnO doping and properties
- Copper Interconnects and Reliability
- Lower Extremity Biomechanics and Pathologies
- Tendon Structure and Treatment
- Plasma Diagnostics and Applications
- Balance, Gait, and Falls Prevention
- Diabetic Foot Ulcer Assessment and Management
- Nanowire Synthesis and Applications
Fudan University
2022-2025
State Key Laboratory of ASIC and System
2023-2024
Shanghai Fudan Microelectronics (China)
2023-2024
In this work, a novel self-aligned source/drain confinement (SA-SDC) scheme is proposed to enable the downsizing of gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs). Compared with traditional diamond-shaped (S/D) epitaxy, SA-SDC suppresses lateral over expansion and facilitates wrap-around contact (WAC) formation, resulting in decrease device area, parasitic capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The effect of the source/drain compressive stress on mechanical stability stacked Si nanosheets (NS) during process channel release has been investigated. in stacking direction increased first and then decreased by technology computer-aided design (TCAD) simulation. finite element simulation showed that caused serious deformation nanosheets, which was also confirmed experiment. This study proposed a novel utilized multi-step etching to remove sacrificial SiGe layers instead conventional...
In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The BDI flow is compatible the main process NS-GAA transistor fabrication provides large window fluctuations, such as thickness S/D recess. It an ingenious solution to insert material under source,...
In advanced CMOS technology, a suitable spacer scheme is crucial to alleviate the effects of increasing parasitic resistance and capacitance on device performance as critical dimensions shrinking. Low dielectric constant (low-k) films, possessing tunable k value ranging from 3.5 6.5, were fabricated using plasma-enhanced atomic layer deposition in single chamber. The fabrication process involved SiN film via SiH2I2 with N2 plasma, well SiOX, SiOCN, SiON films diisopropylamino silane O2,...
Local pain around the ankle joint is a common symptom in patients with chronic instability (CAI). However, whether local would impose any influence on balance control performance of CAI still unknown.A total twenty-six subjects were recruited and divided into following two groups: pain-free (group A) pain-present B). Subjects both groups received independent tests: star excursion test single-leg stance test, order to reflect their ability more accurately.Compared group A, B showed...
Gallium nitride (GaN)-based digital integrated circuits (ICs) are constructed on the commercially available GaN-on-Si wafer designed for pGaN gate HEMT. The functions of inverter, NAND, AND, NOR, and OR logic successfully realized based direct-coupled field-effect transistor (DCFL) structure. Under a drive voltage 5V load ratio 20, low output (VOL) can reach as 0.1V. Additionally, functional-oriented driver, SR flipflop, NOR D flipflop constructed. All transient tests at frequency 100 kHz...
In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic process consisting an oxidation treatment step is proposed used SiGe etching. The exhibits slower rate higher selectivity compared to the direct process. cycle Recipe 1, which has 0.98 nm/cycle, cavity etch. achieved good interlayer uniformity depth (cavity ≤ 5 ±...