Min Su Kim

ORCID: 0000-0003-4939-2829
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About
Contact & Profiles
Research Areas
  • Technology and Data Analysis
  • Advanced Data Storage Technologies
  • Internet of Things and Social Network Interactions
  • Customer Service Quality and Loyalty
  • Semiconductor materials and devices
  • Cellular Automata and Applications
  • Educational Systems and Policies
  • Age of Information Optimization
  • Innovation in Digital Healthcare Systems
  • Educational Research and Pedagogy
  • Network Security and Intrusion Detection
  • IoT and Edge/Fog Computing
  • Software-Defined Networks and 5G
  • Energy and Environmental Systems
  • Education and Learning Interventions
  • Energy Efficient Wireless Sensor Networks
  • Diverse Topics in Contemporary Research
  • Cognitive Functions and Memory
  • IoT Networks and Protocols
  • Consumer Perception and Purchasing Behavior
  • IPv6, Mobility, Handover, Networks, Security
  • Low-power high-performance VLSI design
  • Advanced Image and Video Retrieval Techniques
  • Educator Training and Historical Pedagogy
  • Advanced Memory and Neural Computing

University of Minnesota
2020-2025

Samsung (South Korea)
2009-2024

Daegu Gyeongbuk Institute of Science and Technology
2021-2024

Kyungpook National University
2024

Kyonggi University
2012-2023

Korea Electronics Technology Institute
2023

Sun Moon University
2023

Joongbu University
2021-2022

SK Group (South Korea)
2022

Ontario Stroke Network
2021

We propose SeCReT to ameliorate this problem. is a framework that builds secure channel between the REE and TEE by enabling processes use session keys in regarded as unsafe region. provides key requestor process only when requestor’s code control flow integrity are verified. To prevent from being exposed an attacker who already compromised kernel, flushes memory every time processor switches into kernel mode. In paper, we present design implementation of show how it protects REE. Our...

10.14722/ndss.2015.23189 article EN 2015-01-01

Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], 3b/cell 3D has seen areal density increases more than 50% per year due to aggressive development 3D-wordline-stacking technology. This trend been consistent for last three consecutive years [2-4], however storage market still requires higher diverse digital applications. A 4b/cell technology is one promising solution increase bit [5]. In this paper, we propose with 12MB/s...

10.1109/isscc.2018.8310323 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2018-02-01

In the past few years, various 3D NAND Flash memories have been demonstrated, from device feasibility to chip implementation, overcome scaling challenges in conventional planar [1-3]. The difficulties include shrinking cell and increasing manufacturing costs due quadruple patterning extreme ultraviolet lithography, motivating development of next-generation node beyond 16nm-class [4]. this paper, as a new memory with lower cost superior scalability, we present true 128Gb 2b/cell vertical-NAND...

10.1109/isscc.2014.6757458 article EN 2014-02-01

Data storage is one of the hottest discussion topics in today's connected world. The amount data growth expected to be exponential, while budget and space remain constricted. Since transformation device from planar NAND 3D V-NAND [1], areal density semiconductor devices has continuously evolved surpassed magnetic hard drives. By providing largest capacity smallest footprint, been leading center revolution recent years. However, 3D-technology scaling faces several technical challenges [2]....

10.1109/isscc.2019.8662493 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2019-02-01

Triple-level-cell (TLC) NAND has prevailed the non-volatile memory market, yet quad-level-cell (QLC) is emerging as a suitable replacement for low-cost and high-density storage. However, despite its cost effectiveness QLC's market share not increasing quickly, only due to worse reliability but also slow sequential random read performance. To increase performance an independent plane operation been introduced [1], [2], pass voltage noise, caused by high I/O data-path current consumption,...

10.1109/isscc42614.2022.9731785 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2022-02-20

Accurate prediction of the Remaining Useful Life (RUL) lithium-ion batteries is essential for ensuring safety, reducing maintenance costs, and optimizing usage. However, predicting RUL challenging due to nonlinear characteristics degradation caused by complex chemical reactions. Machine learning allows precise predictions latent functions relationships based on cycling behavior. This study introduces an accurate approach feature engineering DLinear, applied dataset from NASA's Prognostics...

10.48550/arxiv.2501.11542 preprint EN arXiv (Cornell University) 2025-01-20

10.33778/kcsa.2025.25.1.133 article EN Jouranl of Information and Security 2025-03-31

NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents 128Gb multi-level cell (MLC) 150 cells/string structure in 14nm CMOS that can be device. also introduces several approaches to compensate for reliability and degradations caused by the transistors structure. A technique was developed suppress background pattern dependency (BPD) applying low voltage upper word lines (WLs) - drain side(SSL side) WLs respect location of selected WL...

10.1109/isscc.2016.7417945 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2016-01-01

An outdoor delivery robot requires autonomous navigation technologies, such as map generation, driving area definition, path and control. However, integrating the technologies of each field can be difficult due to verification in different experimental environments hardware. This study presents a viable approach for mobile robots by mapping, planning, experiments using Autoware with low-cost LiDAR sensor. To achieve this goal, we compare performance various SLAM algorithms generate precise...

10.1109/tiv.2024.3395615 article EN IEEE Transactions on Intelligent Vehicles 2024-01-01

In cloud computing framework, the data security and protection is one of most important aspects for optimization concrete implementation. This paper proposes a reliable yet efficient FPGA-based system via crypto engines Physical Unclonable Functions (PUFs) big applications. Considering that FPGA or GPU-based accelerators are popular in centers, we believe proposed approach very practical effective method computing.

10.1109/mdat.2017.2741464 article EN IEEE Design and Test 2017-08-18

The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs needed to meet this demand. Furthermore, GPU performance is becoming increasingly important as game graphics requirements pushing limits of capabilities. For an enhanced user experience, a multi-core required. CPU/GPU power efficiency longer battery life has been major interest consumers many years. In order support higher and efficiency, two quad-core with different...

10.1109/isscc.2015.7063105 article EN 2015-02-01

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, cell size Flash has scaled down by merely 50% doubling each per [1] However, side effects arisen distribution reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing...

10.5573/jsts.2011.11.2.121 article EN JSTS Journal of Semiconductor Technology and Science 2011-06-30

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture scaling word-line (WL) transistor....

10.23919/vlsit.2017.7998171 article EN Symposium on VLSI Technology 2017-06-01

Trendy suggestions for learning-based elastic warps enable the deep image stitchings to align images exposed large parallax errors. Despite remarkable alignments, methods struggle with occasional holes or discontinuity between overlapping and non-overlapping regions of a target as applied training strategy mostly focuses on overlap region alignment. As result, they require additional modules such seam finder inpainting hiding filling holes, respectively. In this work, we suggest Recurrent...

10.1109/wacv57701.2024.00397 article EN 2022 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV) 2024-01-03

As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density low-cost devices. Two different approaches meet these requirements are increasing data per cell area scaling. 3b/cell or 4b/cell memories were introduced an effective way lower cost. However, devices suffer from program performance degradation since tighter Vth distribution required. On other hand, scaling...

10.1109/isscc.2011.5746282 article EN 2011-02-01

As near field communication technologies develop rapidly and the supply ratio of smart phones gets higher, scope to utilize NFC(Near Field Communication) is gradually increasing. It tries propose service inform you parking location traffic line with mobile management system which combines these NFC IPS(Indoor Positioning System) for congestion convenience buildings combination IT construction technologies.

10.1109/icisa.2013.6579325 article EN 2013-06-01

10.14313/jamris_3-2018/19 article EN Journal of Automation Mobile Robotics & Intelligent Systems 2018-12-01

We have developed a 64Gb MLC NAND Flash using sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve rate, we introduce slim transistors of ~3 nm-thick gate oxide and dual poly gate, in addition conventional transistors. Furthermore, some new novel circuitry has been implemented, such as Split Power Page Buffer, Local Sense-Amplifier (LSA) Data In/Out Architecture, Regulated Widlar Reference Generator Low VCC Row Decoder.

10.1109/imw.2012.6213644 article EN 2012-05-01
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