Excellent long term reliability InGaP/GaAs heterojunction bipolar transistors (HBT) grown by metalorganic chemical vapor deposition (MOCVD) are demonstrated. There were no device failures (T=10000 h) in a sample lot of ten devices (L=6.4 μm ×20 μm) under moderate current densities and high-temperature testing (J/sub c/=25 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , V/sub ce/=2.0 V, Junction Temp =264/spl deg/C). The dc gain...

Growth of large-area single-crystal silicon on an insulator is achieved by a zone melting technique using halogen lamps. The single-crystal, typically 3–4 mm several centimeters, composed subgrains showing no internal defects, with boundaries parallel to the scan direction. crystallographic orientation (001) along normal film plane and (100)

We describe a technique for measuring minority-carrier lifetime on very small area of material and apply this to recrystallized silicon layers an insulating substrate where the localization crystalline defects gives rise defect-free regions actually used devices. The method uses depletion-mode transistor in which drain-source conductance yields signal equivalent capacitance signal, thus allowing measurements conventional Zerbst transient be made regions.

Halogen lamps have been used to recrystallize polycrystalline silicon deposited on SiO2. 〈100〉 single crystals obtained. 100–200 μm wide subgrains are present in the recrystallized films. We results of a structural analysis defects by using essentially Transmission Electron Microscopy. can classify as follows: primary subgrain boundaries misfit dislocations resulting from low angle misorientation between adjacent growing regions. Secondary related strain films during recrystallization. find...

GaAs single junction solar cells were fabricated on epitaxial liftoff (ELO) 4:″ wafers. 1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> have been with a yield ≫80% across full 4″ ELO Photoluminescence studies of wafers showed no evidence residual strain in the layers as indicated by peak at 870 nm 300 K. Transmission electron microscopy threading dislocations, voids or delaminating semiconductor-metal interface. Quantum efficiency...

Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected expected to lead improved logic devices, memories, CPUs, photosensors (Akasaka, 1986). These require high-density vertical interconnections (3D vias) comparable in aspect ratio present multilevel vias (Reber Tielert, 1996). We have constructed tested 3D ring oscillators fully parallel 64/spl times/64 pixel sensors using a assembly technology which utilizes SOI...

Nondestructive characterization of high-dose oxygen implanted and 1350 °C annealed silicon-on-insulator structures has been performed by spectroscopic ellipsometry. This method provides a fully in-depth profiling (thickness nature) the structure including interfaces. Results have confirmed other techniques such as cross-sectional transmission electron microscopy high-resolution Rutherford backscattering spectroscopy.

AlGaAs emitter heterojunction bipolar transistors (HBTs) are demonstrated to have excellent dc and RF properties comparable InGaP/GaAs HBTs by increasing the Al composition. Al/sub 0.35/Ga/sub 0.65/As/GaAs exhibit very high current gain at all bias levels, exceeding 140 25 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> reaching a maximum of 210 26 kA/cm (L=1.4 μm×3 μm, R/sub sb/=330 /spl Omega///spl square/). The temperature...

The electrical properties of halogen lamp recrystallized silicon films on oxide-coated Si substrates have been investigated by capacitance technique and transport measurements. Bulk interface defect densities revealed deep level transient spectroscopy are lower than 5×1011 cm−3 1010 eV−1 cm−2, respectively. However, the generation lifetimes order 0.1 μs, obtained from pulsed metal-oxide-semiconductor (MOS) capacitor techniques, cannot be accounted for bulk or surface generation, given very...

During the past several years we have been developing technology for creation of 3D microelectronics. Our circuits are fabricated using standard bulk CMOS processing and then transferred from one wafer to another. The transfer process allows alignment layers. resulting structure consists lower substrate associated circuitry, with or more thin-film circuit layers stacked on top, separated by bonding We developed an interconnection that be electrically connected These interconnections small...

A technique equivalent to the conventional C(V) measurement is developed for silicon-on-insulator technology. depletion mode transistor used. The ID(VG) characteristic and its derivative, i.e., transconductance, allow determination of doping Si film, oxide thickness, fixed charge at both Si/SiO2 interfaces. device can be used in process control without any extra steps.

By using halogen lamps, we have annealed implanted Si wafers and recrystallised deposited poly-Si. A transient anneal was accomplished with a good uniformity on 4 in no redistribution of the dopant profile. shaped spot, obtained 〈100〉 single-crystal Si, over an area 2 mm by several centimetres, SiO2 layer grown substrate, without seeding.

Selective annealing by means of an incoherent light system has been employed to grow single-crystal Si on oxide. This technique allows control the location remaining defects (subgrain boundaries) in <100> recrystallised film.

Summary form only given. The high-temperature behavior of devices and circuits fabricated in ISE (isolated silicon epitaxy) SOI wafers bulk Si is discussed. advantages over under operation result from reduced leakage current due to the absence well junction CMOS reduction source drain body areas. One two orders magnitude for compared equivalent observed at 300 degrees C. At this temperature, reaches several tens microamps. These results indicate high temperature dominated by diffusion...

A silicon-on-insulator (SOI) structure was formed by implanting 150 keV O+ ions into a single-crystal n-type Si. The substrate temperature during implantation maintained at 600 °C. Implanted samples were subsequently annealed in the ambient air 1350 °C for 70 min using halogen lamp oven and analyzed Rutherford backscattering/channeling technique, cross-sectional electron microscopy, high-resolution microscopy. It is shown that resulting dislocation density within top Si layer (105–106/cm2)...

Self-aligned Si MESFETs using tungsten for the gate have been fabricated in lamp-recrystallised silicon-on-insulator materials. Devices with lengths of 1.5μm exhibit a DC transconductance 7.5 mS/mm and calculated cutoff frequency 3.9GHz.

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and silicon film containing transistors makes it possible to realize 3D SPAD at the chip level. In our study, nanostructurated created by an optimized arrangement Shallow Trench Isolation (STI) above photosensitive zone generates constructive interferences consequently increase light sensitivity frontside illumination. A simulation...

It is shown that the thickness of silicon and oxide layers a silicon-on-insulator (SOI) structure can be determined from high-frequency capacitance-voltage measurements. The test device consists Schottky diode in series with Si-oxide-Si capacitor. Si film substrate are n-type. operation this explained for n-type help energy-band diagrams. demonstrated simple implemented as process monitor control.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

Abstract We have built plastic displays for SmartCards by integrating high‐quality, crystalline silicon NanoBlock IC drivers using a Fluidic Self Assembly (FSA®) process. With this low‐cost, high‐volume manufacturing approach, flexible peripheral driver strips are now being readied application to commercial liquid crystal and OLED display products.

Summary form only given. In partially depleted films, an adaptation of the Zerbst technique can be used for depletion-mode MOSFETs by measuring transient drain current. Two different methods analysis this signal are proposed. first method, appropriate fitting procedure experimental curve provides so-called effective generation lifetime. Distinction is made monitoring importance sidewalls which increases from wide to narrow transistors or edgeless multi-edge configurations. The surface rate...

A depletion-mode field-effect transistor is used to determine the electrical characteristics of a silicon-on-insulator (SOI) structure such as Si film doping, fixed oxide charges, and interface trapped charges at Si/SiO2 interfaces. We consider case very thin film, i.e., thickness smaller than maximum depletion layer width. The parameters SOI are derived from drain-source current versus gate voltage transconductance characteristics, provided that back surface accumulated by proper substrate...

Npn abrupt AlGaAs/GaAs heterojunction bipolar transistors with thin base widths (WB) down to 200 Å have been fabricated for the first time, and their collector current-voltage characteristics studied. The experimental results show that surface recombination current bulk are both significantly lower in HBTs than comparable devices 500 width. For HBTS, density is proportional ~WB ~WB2. experiment also showed across a p+ GaAs limited, as expected, by thermal velocity of electrons rather...