A5007326993- Semiconductor materials and devices
- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in PLL and VCO Technologies
- Low-power high-performance VLSI design
- Radio Frequency Integrated Circuit Design
- VLSI and Analog Circuit Testing
Samsung (South Korea)
2022-2023
This paper presents a SAR ADC that uses coarse and fine comparators with dedicated logics asynchronous clock generators. The mutual offset of the are calibrated without compromising power consumption impedance sustained skewed inverters save reference current low short circuit additional CDAC settling time. achieves 63.6dB SNDR at 250MS/s while consuming 0.56mW, resulting in 1.81fJ/c.∙s. FoM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</inf> .
This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in 4-nm CMOS process. A switching-jitter compensation technique is proposed the receiver (RX) to improve timing margins from 0.31 0.37 UI at 16 Gb/s, as it adjusts transition slope of front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation PAM-4 signal, relaxed impedance matching used, where 20 <inline-formula...
Ever-growing applications, such as 5G communication, deep learning, advanced driver-assistance systems (ADAS), and extended reality (XR), have fueled demand for increased computing power per-pin interface bandwidth. Recently, four-level pulse-amplitude modulation (PAM4) has been adopted a solution [1-3]: the throughput is doubled without increasing baud (Nyquist) rate. Compared to conventional non-return-to-zero (NRZ) signaling, PAM4 requires more design effort: varying from precise of I/O...
This paper presents an analog assisted digital LDO achieving high current density and fast response characteristic. A comparator based control method enables over 10x ratio of for regardless PVT condition. The proposed in 3nm GAAFET CMOS technology demonstrated 34.15A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> transient characteristic 38mV droop at 1A/1ns load
This paper presents a two-step SAR ADC that uses coarse and fine comparators with dedicated logics asynchronous clock generators for each comparator to increase the energy efficiency by optimizing reduce output loading of generators. The relative offset two is calibrated redundancy based detection input transistor transconductance controlled correction method without compromising power. A constant impedance skewed inverter saves reference current low short circuit additional CDAC settling...