A5108817235- Advancements in Photolithography Techniques
- Copper Interconnects and Reliability
- Nanofabrication and Lithography Techniques
- Metal and Thin Film Mechanics
- Integrated Circuits and Semiconductor Failure Analysis
- Optical Coatings and Gratings
- Semiconductor materials and devices
- 3D IC and TSV technologies
- Advanced Surface Polishing Techniques
- Robotic Path Planning Algorithms
- Plasma Diagnostics and Applications
- Advanced Optical Imaging Technologies
- Ion-surface interactions and analysis
- Robotics and Automated Systems
- Visual Attention and Saliency Detection
- Robotics and Sensor-Based Localization
- Fluid Dynamics and Thin Films
- Mesoporous Materials and Catalysis
- Adhesion, Friction, and Surface Interactions
- Diamond and Carbon-based Materials Research
- Robotic Mechanisms and Dynamics
- Advanced optical system design
- Advancements in Semiconductor Devices and Circuit Design
- Robotic Locomotion and Control
- Advanced Vision and Imaging
Guangdong University of Technology
2025
Shanghai Jiao Tong University
2022
IBM (United States)
2008-2013
IBM Research - Austin
2010-2011
Massachusetts Institute of Technology
2006-2008
The fusion of infrared and visible images provides complementary information from both modalities has been widely used in surveillance, military, other fields. However, most the available methods have only evaluated with subjective metrics visual quality fused images, which are often independent following relevant high-level tasks. Moreover, as a useful technique especially low-light scenarios, effect conditions on result not well-addressed yet. To address these challenges, decoupled...
On the road to insertion of extreme ultraviolet (EUV) lithography into production at 16 nm technology node and below, we are testing its integration standard semiconductor process flows for 22 devices. In this paper, describe patterning two levels a test chip using single-exposure EUV lithography; other layers were patterned 193 immersion lithography. We designed full-field mask contact first interconnect rule-based corrections compensate specific effects shadowing imaging system flare. The...
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using pattern first interconnect level (metal 1). This device fabrication exercise required development rule-based 'OPC' correct for flare and mask shadowing effects. These corrections applied full-field mask. The resulting 0.25-NA fullfield scanner found provide more than adequate...
The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node device back-end layers demonstrate technology. Use EUV pattern via-levels will allow dark-field masks low densities and postpone day when completely defect-free mask blanks are needed. quality imaging at considerably higher than double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly 2-dimensional...
The surface roughness evolutions of single crystal silicon, thermal silicon dioxide (SiO2), and low dielectric constant film coral in argon plasma have been measured by atomic force microscopy as a function ion bombardment energy, impingement angle, etching time an inductively coupled beam chamber, which the chemistry, flux, incident angle can be adjusted independently. sputtering yield (or rate) scales linearly with square root energy at normal angle; additionally, angular dependence all...
We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at 15 nm technology node by integrating it standard semiconductor process flows because we believe that device integration exercises provide truest test and, same time, highlight remaining critical issues. In this paper, describe use EUV with 0.25 NA Alpha Demo Tool (ADT) to pattern contact and first interconnect levels a large (~24 mm x 32 mm) 22 chip using masks state-of-the-art...
Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role in various integration schemes of chip manufacturing. One function OPLs is to fill pre-existing patterns on the substrate, previously patterned vias, enable lithographic patterning next level. More importantly, OPL resistance reactive ion etch (RIE) processes used silicon-containing materials essential for successful pattern transfer from resist into substrate. Typically,...
Purpose Path planning is a fundamental and significant issue in robotics research, especially for the legged robots, since it core technology robots to complete complex tasks such as autonomous navigation exploration. The purpose of this paper propose path tracking framework hexapod robots. Design/methodology/approach First, robot called Hexapod-Mini briefly introduced. Then algorithm based on improved A* proposed, which introduces artificial potential field (APF) factor into evaluation...
The surface roughness evolution of solid organosilicate glass (OSG) and methylsilsesquioxane spin-on porous low-k films after etching in C2F6∕Ar plasmas was characterized as a function ion bombardment energy, fluence reaching the (or, equivalently, time), impingement angle, plasma polymerization propensity newly designed beam system which chemistry, flux, incident angle can be adjusted independently. A polymerization-induced micromasking mechanism proposed to explain roughening these films....
The impact of etching kinetics and chemistries on surface roughening was investigated by thermal silicon dioxide low-k dielectric coral materials in C4F8∕Ar plasma beams an inductive coupled beam reactor. kinetics, especially the angular yield curves, were measured changing pressure feed gas composition which influence effective neutral-to-ion flux ratio during etching. At low ratios, curves are sputteringlike, with a peak around 60°–70° off-normal angles; at grazing ion incidence angles...
The angular etching yields of polysilicon in Cl2∕Ar plasmas, and dielectric materials (thermal silicon dioxide low-k coral) fluorocarbon have been characterized an inductively coupled plasma beam apparatus. effects ion energy, feed gas composition, source pressure are studied. experimental results showed that these parameters had a significant impact on the resulting yield curve. In particular, curve was more sputteringlike at low and/or effective percentage (Cl2 C4F8), with peak around...
The patterning capability of the directed self-assembly (DSA) a 42nm-pitch block copolymer on an 84nm-pitch guiding pattern was investigated in 300mm pilot line environment. chemoepitaxy created by IBM Almaden approach using brush materials combination with optional chemical slimming resist lines. Critical dimension (CD) uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) DSA were characterized. CD rectification LWR reduction observed. found to be...
Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning a second layer over initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications explored. tone inversion process has application split dark field in addition standard bright applications.
For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pattern was printed first, followed by Sidewall Image Transfer (SIT) technique create the 1X pattern. A block lithography process then used trim this form actual designed In paper, 48nm and 45nm SADP build will be as examples demonstrate patterning scheme. General discussions about provided including: 1) flow of technique, 2) benefits vs. split...
Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning a second layer over initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications explored. tone inversion process has application split dark field in addition standard bright applications.
This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to local interconnect level. M1/V0 dual-damascene used triple split bi-directional M1 and double contact (V0) scheme where are with in each direction, respectively. will provide great design flexibility for advanced logic circuits. The patterning is multiple negative tone development lithography-etch. A memorization layer utilized patterned V0 levels, After transferring two via levels into...
Spacer-defined double patterning was investigated as a option for 20/14-nm logic technology's back-end-of-line (BEOL), and compared with the options of front-end-of-line (FEOL). Negative spacer-defined used to provide less overlay impact variable CD control on metal lines other techniques. Block lithography 2nd exposure able maintain better tip-to-tip tip-to-line fidelity by forming that behave additive etch block. SiO<sub>2</sub> spacer directly deposited resist core-mandrel via...
The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm beyond technology nodes. Unlike positive tone resists which use protected polymer as etch block, must adhere a substrate deprotected matrix; poses adhesion bonding for new patterning technology. This problem can be addressed when these photo are coated on anti-reflective coatings plentiful silicon in them (SiARC), specifically tailored...
Lithographic scaling beyond the 22 nm node requires double patterning techniques to achieve pitch values below 80nm. The semiconductor industry is focusing on development of several process including track-only lithographic processing methods in order reduce cost, cycle time and defects. Initial efforts for expose processes have relied use chemical freeze materials prevent inter-mixing resists, also by means thermal curable materials. These two may be complementary, sense that a very robust...
In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. sidewall process, material deposited directly on resist achieve simplification and cost effectiveness. For patterning, core mandrel CD uniformity is proven be main contributor pitch-walking new lithographic window. Here, aerial image log-slope shown measurable predictor of angle pattern. Through screening illumination optimization,...
The challenges facing back-end-of-line (BEOL) etch are becoming increasingly difficult as shrinking dimensions compounded by new materials integration. As critical decrease, key dimension-related include CD control, trench litho stack aspect ratios, RIE lag, and LER. move to low k ultra dielectrics requires the consider sensitivity of films compositional modification, polymer interactions with pores, diffusion effects possible porous materials. minimum pitch reaches sub-100nm, need be...
A novel back-end-of-line (BEOL) patterning and integration process termed Multi-Level Multiple Exposure (MLME) technique is herein introduced. The MLME simplifies BEOL dual damascene (DD) while simultaneously being applicable to all levels. It offers a resolution reaching into the sub-100nm region improves semiconductor manufacturing cost throughput. employs dual-layer imaging stack (via + trench resists) cast onto customized etch transfer multilayer stack. This implements strict...
1 Department of Chemical Engineering, Tsinghua University, Beijing 100084, China 2Department Bio-Nano-Science and Shanghai Jiao Tong 200240, 3 IBM Albany NanoTech Research Development Center, Albany, NY 12309, USA 4College Civil Guangzhou 510006, 5 Applied Chemistry, Tokyo Metropolitan 00813, Japan 6Department Qufu Normal 273165,
With the increasing prevalence of 3D videos, understanding distinctions between 2D and video experiences has become significantly important. In our study, we explored cognitive load imposed by stimuli under various tasks using electroencephalogram (EEG) data. To assess load, introduced Cognitive Load Index (CLI), a measure that combines oscillations theta alpha oscillations. Our experimental setup included four stimuli, each associated with typical tasks. Participants were exposed to both...