To provide a comprehensive understanding of the field effect in silicon nanowire (SiNW) sensors, we take systematic approach to fine tune distance charge layer by controlling hybridization sites DNA SiNW preimmobilized with peptide nucleic acid (PNA) capture probes. Six target DNAs same length, but differentiated successively three bases complementary segment, are hybridized PNA. Fluorescent images show that occurs exclusively on surface between and However, field-effect response sensor...

The BOSCH etch process, which is commonly used in microelectromechanical system fabrication, has been extensively investigated this work for implementation through-silicon via (TSV) technology 3D-microsystems packaging. present focuses on thermo-mechanical stresses caused by thermal loading due to post-TSV processes and their impact the electrical performance of copper interconnects. A test vehicle with deep silicon copper-plated comb structure was designed study evaluate different its...

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before deposition could result significant improvement both leakage current equivalent oxide thickness (EOT). was possible to achieve capacitor with an EOT of 10.5 Å 5.02×10−5 A/cm2 at 1 V bias. X-ray photoelectron spectroscopy analysis indicates...

An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the can greatly prevent formation of unstable germanium oxide at and suppress out-diffusion after electrical measurement shows an equivalent thickness 13.5Å a leakage current 1.16×10−5A∕cm2 1V gate bias achieved TaN∕HfO2∕Ge MOS capacitors with treatment.

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ annealing prior to deposition. By passivation, uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and /spl sim/140% higher peak mobility than of nitridation.

The authors report a method to grow high quality strain-relaxed Ge on combination of low-temperature seed layer low temperature ultrathin Si0.8Ge0.2 buffer with thickness 27.3nm by ultrahigh vacuum/chemical-vapor-deposition without the need use chemical mechanical polish or annealing. On 8in. Si wafer, etch-pit density was 6×106cm−2. root-mean-square surface roughnesses epitaxy atomic force microscopy were 1.4 and 1.2nm for bulk silicon-on-insulator substrates, respectively. Micro-Raman...

Carbon-doped low k thin films were prepared by radio frequency plasma-enhanced chemical vapor deposition at 400°C from polymerization of tetramethylsilane (4MS) and copolymerization silane precursor, with nitrous oxide as the oxidant gas. Copolymer 4MS precursor show much higher rates than polymer 4MS, if all other parameters are kept same. The addition can significantly promote plasma 4MS. structure composition these characterized using Fourier transform infrared X-ray photoelectron...

This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by Si recess etch selective epitaxy of SiC in the S/D regions. carbon mole fraction incorporated is 1.3%. Lattice mismatch /spl sim/0.65% between results horizontal tensile strain vertical compressive channel region, both contributing to substantial electron mobility enhancement. conduction band offset Delta/E/sub c/...

The authors report the performance of selective epitaxial Ge (400nm) on Si-on-insulator p-i-n mesa-type normal incidence photodiodes using ∼14nm low-temperature Si0.8Ge0.2 buffer without cyclic annealing. At −1V, very low bulk dark current densities 1.5–2mA∕cm2 were obtained indicating good material quality, and peripheral surface leakage 14–19.5μA∕cm. For 28μm diameter round photodiode, highest achieved external quantum efficiencies at −5V 27%, 9%, 2.9% for 850nm, 1.3μm, 1.56μm optical...

We demonstrate that a high quality metal organic chemical vapor deposition (MOCVD) HfAl/sub x/O/sub y/ (hereafter HfAlO) dielectric film can successfully be deposited with wide range of composition controllability between HfO/sub 2/ and Al/sub 2/O/sub 3/ in HfAlO using single cocktail liquid source HfAl(MMP)/sub 2/(OiPr)/sub 5/. A ratio 45 to 90% is achieved by controlling process parameters. The effect the on electrical properties also investigated. (10% 3/), which has minimum sacrifice K...

The formation of tungsten nanocrystals (W-NCs) on atomic-layer-deposited HfAlO∕Al2O3 tunnel oxide was demonstrated for application in a memory device. It found that the density and size distribution W-NCs are not only controlled by initial film thickness, annealing temperature, time, but also metal∕tunnel interface structure. Well-isolated with an average diameter 5 nm surface 5×1011cm−2 were obtained applying thin Al2O3 wetting layer onto HfAlO tunneling oxide. A large flatband voltage...

Gate-all-around n-MOSFETs with Si-nanowire (~7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (~5 K to 295 K). I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> -V xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristics at low V (~50 mV) exhibit a decrease in current decreasing temperature strong inversion up about ~200 K. However, high , drain reverts typical behavior, i.e.,...

Phosphorus <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</i> xmlns:xlink="http://www.w3.org/1999/xlink">situ</i> doped (Si <sub xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> ) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source drain regions double-gate -oriented (110)-sidewall FinFETs to induce tensile strain silicon channel....

Germanium (Ge) metal-oxide-semiconductor-field-effect transistors (MOSFETs) have higher carrier mobilities than Si. We studied the growth of high quality single-crystal germanium on insulator (GOI) using rapid liquid-phase epitaxial and defect-necking techniques. Stable Ge was seen at a temperature , below melting point Ge. At above temperature, we found segregating into balls. Defect-free crystals were grown from semisolid state The technique improved with an underlying undercut to minimize...

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the throughput required via slope that is achieve conformal deposition of dielectric, copper diffusion barrier seed metallization. It further shown how a void-free plating achieved for implementation into 3-D integrated systems.

It has been shown that as the aspect ratio of through-silicon vias (TSV) increases, tapering TSV structure greatly helps in achieving good sidewall coverage for dielectric, barrier and copper seed metal layers to eventually achieve a void-free via-filling by electroplating process. In present work, novel three-step tapered via etching process developed demonstrated viable fabricating interconnection structure. This paper discusses great detail about plasma etch mechanisms responsible...

Thermal instability of effective work function and its material dependence on metal/high-/spl kappa/ gate stacks is investigated. It found that thermal the metal electrode a dielectric strongly dependent material. related to presence silicon at interface, Fermi-level pinning position location interface. The silicon-metal or metal-silicon bond formation by anneal metal/dielectric interface induces donor-like acceptor-like states, causing change function.

We report the demonstration of 55 nm gate length strained n-channel field-effect transistors (n-FETs) having an embedded Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> structure that is beneath channel region and which acts as a strain-transfer (STS). The STS has lattice interactions with both silicon source drain regions overlying region. This effectively results in transfer...

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that only Pi-shaped S/D. With the usage longer hydrofluoric acid cleaning time prior selective-epitaxy-raised S/D growth, recess buried oxide formed. This allows subsequent growth on sidewalls regions extend into recessed provide larger compressive stress channel for enhanced...

This paper for the first time, reports memory enhancement characteristics and good retention with feasibility of two-bit operation small scale devices gate length down to 100 nm, using double layer W nanocrystals embedded in HfAlO next generation application. Double device shows increasing window scaling which will be extremely beneficial

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric silicon passivation (SP) surface treatment are extensively investigated. Surface prior to high-K deposition is critical achieve small leakage currents well equivalent oxide thicknesses. SP provides improved interface quality compared the nitridation,...

We report the demonstration of 25 nm gate length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> tri-gate FinFETs with Si xmlns:xlink="http://www.w3.org/1999/xlink">0.99</sub> C xmlns:xlink="http://www.w3.org/1999/xlink">0.01</sub> source and drain (S/D) regions. The strain-induced mobility enhancement due to S/D leads a drive current I xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> improvement 20% at fixed off-state...