A bottom-up circuit clustering step is one of the most significant steps in reconfigurable systems-on-chip design flow. Qualitative provides efficiency subsequent placement and routing steps. The goals are following: a) achieving high density by minimizing number clusters; b) decreasing time delays localizing time-critical connections within a cluster using fast local resources. There several popular solutions to these issues such as partitioning algorithms, heuristic algorithms. In this...

Reconfigurable system-on-chip (RSoC) is an integrated circuit that contains reconfigurable logic blocks and hard IP cores, such as microprocessors, RAM, LVDS, multipliers, etc. For successful RSoC design one needs a high-quality CAD system implementing new multilevel placement routing approaches take into account the natural hierarchy of devices. Placement most important complex stages in flow impacts main characteristics digital circuits. We developed two-level algorithm for initial...

Placement is one of the most difficult stages reconfigurable system-on-chip design flow.Designing highspeed systems requires efficient timing-driven placement algorithms.In this article we present a new algorithm based on simulated annealing method for island-style RSoC.Since RSoC hierarchical, our divided in two stages: global and detailed.At stage place groups logic elements (GLE) with respect to assigned input/output cells macroblocks.At detailed inside each GLE.We developed cost function...

Reconfigurable system-on-chip (RSoC) is a device that contains configurable logic blocks and hard IP cores in the single chip. Designing high-speed digital circuits RSoC requires efficient timing-driven placement algorithms. In this article we present new algorithm based on simulated annealing method for island-style reconfigurable system-on-chip. We developed novel cost function half-perimeter wire length delay model. Lookup matrices both global local interconnections are used to accurately...

Hierarchical field-programmable gate arrays (FPGAs) consist of an array programmablelogic blocks arranged into groups. Successful routing requires optimal placement logic elementswithin the groups, considering architectural features local interconnections. Classicalalgorithms are not able to consider these features. That’s why, development new algorithmsis required. In this paper, we present a detailed algorithm with metric thatallows us estimate number available interconnections inside...

A two-level approach is one of the most popular approaches to placement for island-style FPGAs. First, an initial generated, then optimization based on a simulated annealing method performed. The algorithm can strongly affect convergence rate and quality final solution. This paper focused development analysis new methods. Five algorithms are considered: random, force-directed, input/output ranking, line-by-line. Input/output ranking place logic elements ranks, where element's rank length...

The problem of analyzing and evaluating the structure FPGA routing resources at early stages design flow presents great interest for researchers. Until now, an approach, consisting in passing full (logic synthesis, placement, routing) on a set test circuits with subsequent estimation various parameters each architecture being analyzed, had been dominant. Despite high accuracy, this approach has long runtime requires lots computing resources, as well CAD tuned to analyzed architecture. Modern...

The problem of FPGA architecture routability evaluation has always attracted the designers' attention. Nowadays most chip delay and area is due to routing wires switches that make accurate efficient very important. Traditionally architectures have been studied using experimental techniques. However, a full CAD flow time-consuming requires tuning given architecture. Therefore, more attention paid various metrics, models algorithms allow without design flow.Wotan modern tool allows designers...

This paper focuses on the development of trusted tools for designing digital circuits in basis heterogeneous field programmable gate arrays (FPGAs). Designing FPGAs is one most actively growing areas Russian microelectronics at present. The discusses main problems and challenges associated with computer-aided design tools. authors propose a relevant approach to system based use open-source software together proprietary developments its critical components. allows increase efficiency...

Searching for new ways to improve the efficiency of integrated circuits (IC) led development specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation standard cell library, containing ready-to-use IP cores along with cells. Specific customer designs require flexibility IC’s architecture and, therefore, automatic CAD clustering placement algorithms configuration. The efficient configuration methods impossible without relying on...