A5010846099- Radio Frequency Integrated Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- CCD and CMOS Imaging Sensors
- Analog and Mixed-Signal Circuit Design
- Sensor Technology and Measurement Systems
- Advancements in PLL and VCO Technologies
- Bluetooth and Wireless Communication Technologies
- Advanced Power Amplifier Design
- Non-Destructive Testing Techniques
- Cloud Computing and Resource Management
- IoT and Edge/Fog Computing
- Microwave Engineering and Waveguides
- Electrostatic Discharge in Electronics
- Magnetic Field Sensors Techniques
- Caching and Content Delivery
LG (South Korea)
2020
Sungkyunkwan University
2015-2018
Seoul National University
2004
A dual-mode transceiver integrates the transmitter of 0-dBm output power and receiver for both Bluetooth with -87 dBm sensitivity 802.11b -86 in a single chip. direct-conversion architecture enables maximum reuse optimal current consumption various building blocks each mode low-cost low-power solution. single-ended power-amplifer (PA) driver transmits nominal 0 18-dB gain control 3-dB steps. Only little area overhead is required baseband active filter programmable amplifier (PGA) to provide...
A compact CMOS linear transconductance (LiT) voltage‐controlled oscillator (VCO) in 65 nm process is presented. The proposed LiT technique realised using NP core without a choke inductor to reduce die area and avoid dual resonance problem. measured output frequency of the VCO shows 11.18–11.98 GHz phase noise −112.62 dBc/Hz at 1 MHz offset frequency. DC power consumption buffer 5.86 6 mW, respectively. It achieves high figure merit normalised 198.6 dBc/Hz.
A dual-mode direct-conversion transceiver integrates the transmitter of 0dBm output power and receiver for both Bluetooth with -87dBm sensitivity 802.11b -86dBm in a single chip all building blocks shared low cost solution. Fabricated 0.25/spl mu/m CMOS process, die size is 8.4mm/sup 2/ including pads current consumption RX 50 mA 65mA 802.11b.
This paper proposes a 10-b 10MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) structure using Vcm based capacitive digital-to-analog (CDAC). In the proposed DAC, switching is always straightforward and MSB decided without any energy. The input sampled at bottom plate of CDAC as it provides better linearity. Comparator applies adaptive power control to reduce consumption. For further reduction, accuracy comparator for coarse fine bits are different reconfigurable...
This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with shared Multiplying DAC. Using MDAC, the total capacitance in SAR decreased by 93.75%. The proposed consumed 2.28mW under 1.2V supply and achieved 9.679 bit ENOB performance. was implemented 0.13μm CMOS technology. chip area 760 × 280 μ㎡.
Power grid design is one of the key challenges in large SoC design. In order to guarantee robustness power grid, dynamic IR drop should be analyzed correctly. this paper, we have described weakness vectorless analysis and necessity vector-based analysis. We improved coverage for more accurate The results were obtained with FinFET technology node all simulations done ANSYS RedHawk.
HTML5 Smart Virtual Machine is a virtual machine based solution to executing contents on various platforms such as PC, TV, and mobile devices by web browsers that support HTML 5. This 5 SVM has an advantage machine, but the VM execution method raise problem performance. paper proposes offloading solve this performance enhancement of with cloud system. By proposed method, enhanced its extremely using server side complexed time consumed functions.