A5052287467- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Energy Harvesting in Wireless Networks
- Analog and Mixed-Signal Circuit Design
- Wireless Power Transfer Systems
- Advanced DC-DC Converters
- Electromagnetic Compatibility and Noise Suppression
- Multilevel Inverters and Converters
- Innovative Energy Harvesting Technologies
- Bluetooth and Wireless Communication Technologies
- CCD and CMOS Imaging Sensors
- Low-power high-performance VLSI design
- Advanced Battery Technologies Research
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Interconnection Networks and Systems
- Advanced Sensor and Energy Harvesting Materials
- Advanced Optical Sensing Technologies
- Induction Heating and Inverter Technology
- Photovoltaic System Optimization Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Power Line Communications and Noise
- Embedded Systems Design Techniques
- Power Systems and Renewable Energy
Samsung (South Korea)
2025
Sungkyunkwan University
2014-2021
This paper presents a full-CMOS wireless power receiving unit (WPRU) with high-efficiency 6.78-MHz active rectifier and dc-dc converter for magnetic-resonant alliance (A4WP) applications. The proposed delay-locked loop (DLL) is highly efficient receiver circuit intended use in resonant charging applications frequency of 6.78 MHz. Each MOSFET the turned on off based ac input voltage. delay between current voltage due to delays internal blocks such as limiter, level shifter, gate driver,...
This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through coarse counter, middle, fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle delay-locked loops (ADDLLs) is provided to ensure stability of generated slots. Charge pump, loop filter, voltage-controlled line inside conventional analog (DLLs) are...
This article presents a power-efficient hybrid energy-harvesting system that scavenges energy from solar, vibration, and radio frequency (RF) sources converts into regulated output dc voltage courtesy buck–boost dc–dc converter. The proposed architecture incorporates tetra-paths for maintaining high power conversion efficiency (PCE) over extended input range (−10 to 30 dBm). A time-domain maximum point tracking technique is solar harvester. high-efficiency full wave rectifier designed...
This paper presents a low-power frequency-shift keying (FSK) transmitter (TX) with an all-digital phase locked loop (ADPLL) based on direct modulation for use in Bluetooth low energy application. A power ADPLL Retimer, 2-stage time to digital converter, and gain estimation technique is proposed achieve FSK at 1 Mbps data rate. high-efficiency class-D amplifier, dual output modes ramping filter (RDF), reduce the spurious tones. The TX implemented 1P6M 55-nm CMOS technology die size of 0.53 mm...
In this article, a 15-W quadruple-mode reconfigurable wireless power-receiving unit with high efficiency for Inductive coupling and magnetic resonance-based standards, such as power consortium (WPC), matters alliance (PMA), (A4WP), secure transmission (MST) applications is proposed. Quadruple-mode gate controller(QMGC) proposed in synchronous rectifier to manage sizes of core drivers which results maximum conversion (PCE) each mode based on conduction switching losses. QMGC, switchable zero...
This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth energy application. To ensure that the proposed can operate at 1 Mbps data rate, is implemented using an all-digital phase locked-loop technique. The to share antenna matching network between transmitter receiver, thus minimizing system cost by reducing external components. 1P6M 55-nm CMOS technology. die area of DC-DC converter 1.79 mm <sup...
Solar cell is one of the most important new renewable energy sources for future generation. This paper presents a novel two stage DC/DC converter topology photovoltaic (PV) power conditioning systems (PCSs). The proposed consists an interleaved boost and two-tank LLC resonant which connected in parallel primary series secondary. main idea that system can achieve either unilateral or bilateral operations along with level output voltage from PV module, accordingly leads to enhanced performance.
This paper presents an inductive coupling wireless power receiver with high efficiency active rectifier and multi feedback LDO regulator. The synchronous the zero current sensing is proposed to achieve minimizing reverse leakage current. Multi Feedback regulator implement output voltage regulation, over protection, limit, adaptive communication limit sharing single transistor. chip implemented using 0.18 μm BCD technology area of 4.0 mm × mm. maximum conversion Active Rectifier 94.2 % when...
This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) Continuous Tracking (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, need Time-to-Digital Converter (TDC) is eliminated providing CFTL circuitry. feature makes design compact, suitable IoT The based on synthesizable pulse injection frequency-locked loop along with ultra-low-power LC...
This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with shared Multiplying DAC. Using MDAC, the total capacitance in SAR decreased by 93.75%. The proposed consumed 2.28mW under 1.2V supply and achieved 9.679 bit ENOB performance. was implemented 0.13μm CMOS technology. chip area 760 × 280 μ㎡.
This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth energy application. To ensure that the proposed can operate at 1 Mbps data rate, is implemented using an technique. The to share antenna matching network between transmitter receiver, thus minimizing system cost by reducing external components. 1P6M 55-nm CMOS technology. die area of DC-DC converter 1.79 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In this paper, an ultra low power, fully synthesizable digital phase and frequency detector (DPFD) is presented for all lock loop (ADPLL) applications in bluetooth energy (BLE) transceiver. The adaptation technique applied the fractional feedback to achieve highly accurate target of digitally controlled oscillator (DCO). range extension feature facilitates DCO generate stable under severe noise. polarity control different BLE channels also incorporated proposed design. external mode...
This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth energy application. To ensure that the proposed can operate at 1 Mbps data rate, is implemented using an technique. The to share antenna matching network between transmitter receiver, thus minimizing system cost by reducing external components. 1P6M 55-nm CMOS technology. die area of DC-DC converter 1.79 mm2. consumption Tx Rx are 6 5 mW, respectively. noise figure...
This paper presents a Spread Spectrum Clock Generator (SSCG) based on Relaxation oscillator using Up/Down Counter. The current is controlled by counter and the spread spectrum of Oscillator. A Oscillator with temperature compensation BGR ADC presented. to determine frequency can be controlled. output compensated adjusting according code that from BGR. EMI Reduction SSCG 11 dB, down 150 kHz. consumption <TEX>$600{\mu}A$</TEX> 5V operating 2.3 MHz 5.75 MHz. rate change was approximately...
This paper presents a fast lock mixed-mode DLL (delay-locked loop). The architecture of the proposed uses coarse-step TDC (time-to-digital converter) scheme and an analog feedback loop, which is fine step. A simple technique to phase blend DDL (dual delay lines) with difference in coarse step improves time resolution without additional time. Based on this improved resolution, second can be completed provide time, high accuracy low power consumption. operates clock frequency range 0.6GHz 2GHz...
This paper, we implemented a method to compensate the internal offset in instrumentation amplifier structure. The proposed current sensor is used wireless power transmitter where input voltage changed. In order lower voltage, resistor dividing performed at terminal of amplifier. When occurs circuit using this closed-loop changed open-loop and output confirmed calibration generated circuit. We within +5 % error rate occurring resistor. designed with 180 nm BCD process it converts 0 ~ 1.8 V by...
This paper presents a modeling of All Digital Phased-Lock Loop (ADPLL) based on reference injection (RI) technique in Lab View. ADPLL is one the attractive solutions due to its low design complexity and power consumption which makes it suitable candidate for IoT devices. The RI eliminates strict requirements time digital converter (TDC) traditional structure significantly reduces consumes power. By utilizing efficient system capabilities offered by LabVIEW environment, modeled evaluate...
In this paper, we propose a replica-based all digital delay locked loop(ADDLL). the ADDLL, phase detector detects error, and accumulator(ACC) determines how long output clock leads to or delays input clock. addition, analog charge pump, loop filter(LF), voltage controlled line are replaced by ACC digitally line(DCDL), thereby decreasing leakage current size of LF. study, ADDLL uses replica DCDL describe technique for detecting error that may be caused changes in temperature supply after DLL...