This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through coarse counter, middle, fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle delay-locked loops (ADDLLs) is provided to ensure stability of generated slots. Charge pump, loop filter, voltage-controlled line inside conventional analog (DLLs) are...

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which sensor node monitors the received adaptively controls single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes radio frequency (RF) energy between harvesting (EH) path decoding (ID) path. The proposed SWIPT enables self-powering an ID above 20 dBm input power, leading to...

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates deep triode region of active part VCO, lowers introduced by gm-cell. switch sizes inside switched capacitor bank VCO are optimized to minimize resistance switches while keeping wide tuning range. A new layout shortens routing outputs, parasitic inductance routing. presented method prevents reduction quality...

In this article, we present an integrated triple-mode wireless power transmitter unit (TWPTU) circuit supporting all three alliance for (A4WP), consortium (WPC), and matters (PMA) standards, simultaneously, high-efficiency battery charging application. The amplifier (PA) utilizes the adaptive gate splitting technique free-wheeling control to achieve high efficiency in triple modes. programmable supply voltage from two dc–dc converters supplies PA. output of PA is measured by proposed...

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of structure, choppers are used every stage high gain amplifiers. Besides, required area and power, only CIC filter structure adopted as decimation filter. has configurable that can be different data rates input bandwidths. The...

This article presents a 2.4 GHz and high-efficiency wireless power receiver (Rx) integrated with low-power transmitter (Tx) for charging of the Internet-of-Things (IoT) or wearable devices. A single pole double throw (SPDT) circuit isolates operation Rx from Tx, thereby offering capability sharing antenna between them. The employs radio frequency (RF)-dc converter, which is facilitated threshold voltage cancellation technique enhancing efficiency, adjustable internal impedance matching...

This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) control line (DCDL) during phase locking which utilizes less power and area as compared analog (DLL). In lock state, ACC value dithers due closed operation. A controller is proposed detect performs cancelation selects optimum controlling replica DCDL TDC It helps jitter reduction...

This paper presents an integer-N phase-locked loop (PLL) for RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with DC-DC converter, and bias-controlled charge pump feedback are proposed. The frequency range of VCO is 4.5–6.1 GHz, target proposed PLL 2.4 5.8 GHz in industry–science–medical band. It designed same phase margin bandwidth using one filter. consumes less than 8 mW from...

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, satisfy required specifications. switch applies six stacks series shunt transistors as big 3.9 mm/160 nm 0.75 nm, respectively. A negative charge pump voltage booster generate boosted control voltages improve harmonics keep Inter-Modulation Distortion...

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for wireless power transfer system. is four–channel SAR ADC structure with 10-bit resolution each channel, which can also be applied as single 12-bit ADC. To reduce the area and number of required devices in module, hybrid-type capacitor resistor DACs applied, DAC shared between channels determines seven least significant bits (LSB)s, while three most (MSBs). For operation mode, to...

This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) Continuous Tracking (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, need Time-to-Digital Converter (TDC) is eliminated providing CFTL circuitry. feature makes design compact, suitable IoT The based on synthesizable pulse injection frequency-locked loop along with ultra-low-power LC...

In the proposed low-jitter delay locked loop (DLL), analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve problem achieving small gains mirroring currents. Also, leakage currents during lock state removed when DAC provides a fixed voltage based on ACC's output digital code. A simple detector utilized deactivate ACC generate control for elements locks. Another also applied dynamically loop-gain time. Loop-Gain decreases...

In this paper, a Radio Frequency (RF) energy harvester (EH) system for Internet of Things (IoT)-related applications is presented. The proposed EH architecture operates at 5.2 GHz band and utilizes multiple rectenna. This approach enhances the efficiency whole over wide dynamic RF input range. presented circuit, configuration rectenna controlled by Field-Programmable Gate Array (FPGA) with respect to power level received signal. addition, an automatic adaptive matching based on rectenna,...

This paper presents a 5.8 GHz highly sensitive, high-dynamic-range RF receiver front-end with Automatic-Gain Control (AGC) and high image-rejection for Dedicated Short-Range Communication (DSRC) application. It is formed by transceiver common matching, single to differential Low-Noise Amplifier (LNA), an active mixer Image Rejection Filter, AGC unit. The proposed unit composed of power-detector over the intermediate-frequency signals downconverter mixer. power detector produces wide dynamic...

Design of a 12-bit Pipeline Analog to Digital Converter (ADC) with 40 MS/s sampling rate using proposed modified Operational Amplifier (OP-AMP) is presented in this paper. The ADC architecture, consists eleven pipeline stages ten 1.5-bit pipelined and one flash 2-bits resolution. This design implemented by the 90-nm CMOS process. power consumption reduced various techniques, including sample hold (SH) less OP-AMP sharing technique, capacitor size scaling ADC. FFT analysis which results...

This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with dynamic range from 47.5 to 80 MHz. To reduce power consumption and improve energy efficiency, this work employs only one comparator capacitor generate output clock in comparison conventional structures. A total 50% ± 5% duty cycle is obtained for by implementing an auxiliary comparator. The proposed uses voltages external low-dropout (LDO) voltage bandgap reference (BGR) required supply voltages,...

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and dual-mode ultra-low noise TIA 142-dBΩ towards the maximum gain. The required high sensitivity of signal conditioning path dictates having at while Input-Referred Noise (IRN) is kept low. Therefore, to detected current bio-signals provided by photodiode module. front end formed TIA, DC-Offset Cancellation (DCOC) circuit, Single-to-Differential Amplifier (SDA), two Programmable Gain...

This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for Bluetooth Low Energy (BLE) application. In order to reduce the number of capacitors in Capacitor Digital Analog (CDAC), split type DAC has been applied VCM-based switching scheme. Applying this, unit each CDAC reduced by over 14 times. reduces area which is dominated CDAC. Also, input and reference buffers design specifications are relaxed, mismatch reduced. The conversion...

This paper presents a dual-mode adjustable-high-gain transimpedance amplifier (TIA). The TIA is designed with high sensitivity to current bio-signals for fine-dust detection system Integrated Circuit (IC) based on the operation of photodiode module gain amplifications. Gain adjustment implemented by coarse steps using selective-loads four different values and fine 42 dBΩ during 16 steps. To improve settling time, capacitive compensation applied last stage. An off-state circuitry proposed...

This paper presents a 750 μW fractional-N Phase-Locked Loop (PLL) for Wake-up Receiver (WuR) architecture. The frequency synthesizer operates from 1.5 to 2.3 GHz and the proposed quadrature phase generator provides four local oscillator signals with frequencies of 263 MHz, 433 868 920 MHz. Several techniques are adopted facilitate ultra-low-power operation. Inside Voltage-Controlled Oscillator (VCO), inductance resonance is maximized provide low power consumption capacitor banks optimized...

This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for Bluetooth Low Energy (BLE) application. The objective of this work is to reduce the number capacitors in Capacitor Digital Analog (CDAC). To achieve this, hybrid type DAC has been applied where 8 Most Significant Bits (MSB)s are decided through capacitive and 4 Least (LSB)s Resistor (RDAC). conversion speed design reaches up 6 MS/s. prototype ADC 90 nm complementary metal-oxide...

This paper proposes a reference voltage generator structure based on the difference between threshold voltages (Vth) of standard (SVT) and low (LVT) transistors. The proposed does not apply any passive resistors or bipolar junction transistors (BJT). is designed using 55 nm (shrinked 65 nm) CMOS process achieved temperature coefficient (TC) 1.6-ppm/°C over -40°C to 85°C ranges. power supply rejection ratio (PSRR) for this -93dB.

This paper presents a wide-band multi-level switched mode class-E/F23 Power Amplifier (PA) with reconfigurable power stage core transistor and load reactance compensation part. An Automatic Calibration Scheme (ACS) is proposed to perform the reconfiguration based on algorithm. The PA formed by class-D driver amplifier, cascaded stage, load, ACS its algorithm, matching network at end of before antenna. implemented using 130 nm CMOS technology. wideband operates in frequency range from 470 MHz...