A5075753791- Energy Harvesting in Wireless Networks
- Radio Frequency Integrated Circuit Design
- Advanced Power Amplifier Design
- Wireless Power Transfer Systems
- Full-Duplex Wireless Communications
- RFID technology advancements
- Advanced DC-DC Converters
- Wireless Body Area Networks
- GaN-based semiconductor devices and materials
- Antenna Design and Analysis
- Indoor and Outdoor Localization Technologies
- Advanced Photonic Communication Systems
- Advanced Sensor and Energy Harvesting Materials
- Silicon Carbide Semiconductor Technologies
- Innovative Energy Harvesting Technologies
- PAPR reduction in OFDM
- Electrical Contact Performance and Analysis
- Metamaterials and Metasurfaces Applications
- Perovskite Materials and Applications
- Wireless Communication Networks Research
KU Leuven
2021-2024
Sungkyunkwan University
2019-2022
This paper presents a holistic and authoritative review of the role microwave technologies in enabling new generation wearable devices. A human-centric Internet Things (IoT) covering remote healthcare, distributed sensing, consumer electronics, calls for high-performance devices integrated into clothing, which require interdisciplinary research efforts to emerge. Microwaves, "interconnect" wireless networks, can enable, rather than solely connect, next autonomous, sustainable,...
This paper presents a combined multi-tone simultaneous wireless information and power transfer (SWIPT)/third-order intermodulation (IM3) backscattering architecture. integrated system uses the diode's nonlinear behaviour as well frequency division duplex (FDD) to perform three critical functions: downlink communication, uplink energy harvesting. Measurements of prototype design prove that communication does not affect transfer. A data rate 1 kbps, 4.84 dB IM3 dynamic range, 30% conversion...
In this article, we present an integrated triple-mode wireless power transmitter unit (TWPTU) circuit supporting all three alliance for (A4WP), consortium (WPC), and matters (PMA) standards, simultaneously, high-efficiency battery charging application. The amplifier (PA) utilizes the adaptive gate splitting technique free-wheeling control to achieve high efficiency in triple modes. programmable supply voltage from two dc–dc converters supplies PA. output of PA is measured by proposed...
In this paper a novel batteryless sensor node for IoT applications is proposed. The design combines an energy harvesting circuit with backscattering (EHBS), capable of simultaneously wireless RF and transmitting data to the base station. Consequently, consists two parts: rectifier based on harmonics termination one hand branch consisting bandpass filter circuitry manipulate impedance seen by diode antenna at desired frequencies, other hand. Based such frequency division duplex (FDD)...
This paper presents a combined simultaneous wireless information and power transfer (SWIPT)/third-order intermodulation (IM3) backscattering architecture. The self-interference signal degrades the reliability reading range in base station. An active IM3 backscatterer has been employed to improve signal-to-noise ratio reduce In addition, we have shown both analytically experimentally that proposed frequency modulated improves SWIPT performance. Finally, joint operation with downlink, 10.1 dB...
In the ever-evolving digital landscape, Internet of Things (IoT) devices are transitioning from battery reliance to functioning as battery-less systems. This shift has led innovative energy- and data-transfer methodologies. this context, we introduce a Local Oscillator (LO)-less Simultaneous Wireless Information Power Transfer (SWIPT)-backscatter duplexing system that capitalizes on time-division (TDD) enable coexistence SWIPT backscatter modes. By employing TDD integration, switching...
In this paper, a 5.8 GHz Class-E power amplifier with analog delay cell to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. The consists of 2-stage Class-AB as driver stages and cascode topology PA core. To an 128 core cells implemented which has achieved same fall time rise time, less area simplicity in comparison digital cells. Realized 0.13-μm CMOS technology, achieves 9.5 dBm 57 dBc output adjacent channel ratio, respectively. Occupied...
To address the challenges of energy constraints in Wireless Sensor Networks and Internet Things devices, this study presents an enhanced wake-up receiver for Simultaneous Information Power Transfer applications. The proposed design incorporates a passive 2 × Multiple-Input Multiple-Output antenna configuration, which enhances sensitivity reliability detecting signals under diverse environmental conditions. architecture also includes two-stage rectifier operational amplifier to efficiently...
In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable amplitude shift keying (ASK) and correction factor due to variation compensated adaptively in automatic mode keep constant output power. external mode, the suitable core selection higher design consumes 17.29 nW draws 14.41 nA current from 1.2...
This paper presents a wide-band multi-level switched mode class-E/F23 Power Amplifier (PA) with reconfigurable power stage core transistor and load reactance compensation part. An Automatic Calibration Scheme (ACS) is proposed to perform the reconfiguration based on algorithm. The PA formed by class-D driver amplifier, cascaded stage, load, ACS its algorithm, matching network at end of before antenna. implemented using 130 nm CMOS technology. wideband operates in frequency range from 470 MHz...
This paper proposes a compact three-mode base station capable of performing radar sensing, communication, and wireless power transfer (WPT) in collaboration with indoor sensor networks. With regard to the node, transmits two-tone signals downlink support its operation provides two-way communication. The node sends uplink information through backscattering using third order intermodulation (IM3) product rectification. In mode, single-tone continuous wave (CW) is used monitor if there moving...
This paper presents a novel architecture for low power IoT sensor nodes, integrating backscattering and energy harvesting circuits. The proposed circuit employs bandpass filter (BPF) integrated with an efficient wide-band rectifier variable impedance to create two distinct nearby frequency bands (f<inf>EH</inf>) (f<inf>BS</inf>). For two-tone incident signal total peak of -7 dBm, -16.7 dBm is backscattered while 56.45 μW harvested. Backscattering achieves 10.1 dB dynamic range...
In this paper, a configurable linear ramp controller (CLRC) for power amplifier (PA) is proposed. It changes PA core size linearly amplitude shift keying (ASK) modulation and improves controllability. The ramping reduces harmonics spurious in output spectrum performance. proposed uses standard cells the unit delay it fully synthesizable. step between 0.2 ns to 0.7 ns. needs 51.73 K gate counts its implementation. design consumes 863 μW draws 719 μA current from 1.2 V supply. integrated into...
<p>In this paper, a novel reconfigurable 5.8 GHz linear power amplifier with digital pulse-shaping filter (PSF) to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. An on-chip load transfer network (LTN) able match output variations PA while keeping return loss blow -10 dB. Furthermore, LTN improves stability by varying quality factor of different operation conditions. The consists Class-AB driver stage and cascode topology core. To...
<p>In this paper, a 5.8 GHz linear power amplifier (PA) in 130 nm CMOS process using transconductance linearization technique is presented. The stage consists of main with Class-F load impedance and two auxiliary amplifiers which are biased for weak Class-AB. proposed configuration increases both the linearity PA at high output levels efficiency back-off powers. AM-AM AM-PM nonlinearities cancel same higher A bypass network introduced to prevent positive feedback common-mode...
<p>In this paper, a 5.8 GHz linear power amplifier (PA) in 130 nm CMOS process using transconductance linearization technique is presented. The stage consists of main with Class-F load impedance and two auxiliary amplifiers which are biased for weak Class-AB. proposed configuration increases both the linearity PA at high output levels efficiency back-off powers. AM-AM AM-PM nonlinearities cancel same higher A bypass network introduced to prevent positive feedback common-mode...
<p>In this paper, a novel reconfigurable 5.8 GHz linear power amplifier with digital pulse-shaping filter (PSF) to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. An on-chip load transfer network (LTN) able match output variations PA while keeping return loss blow -10 dB. Furthermore, LTN improves stability by varying quality factor of different operation conditions. The consists Class-AB driver stage and cascode topology core. To...