The design of a triple-band circularly polarized hexagonal slot antenna with L-shaped slits is presented in this study. By adding three slit arms to the slot, radiation achieved at different frequencies. proposed excited by simple tapered microstrip feeding line. A conducting reflector also used enhance gain. measured -10 dB reflection bandwidths are 33.16% (3.22-4.5 GHz) and 22.72% (4.76-5.98 GHz). 3 axial ratio for triple bands 1.7%, 3.86%, 5.23%, respectively. peak gains within 5.5 dBic,...

This paper presents a retention/ pulse frequency modulation (PFM)/ width (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed is capable of handling loads from 10 μA to 20 mA high efficiency by applying triple (retention mode, PFM PWM mode), gate split technique, AZCD. Retention extend wide load range at ultralight load. Gate technique adjusts the conduction loss switching loss. AZCD...

This paper presents a broadband Doherty power amplifier (DPA) design with an octave bandwidth based on new load network consisting of quasi-lumped impedance transformer for the carrier amplifier, multiple resonance circuit peaking and post-matching network. The were designed accurate equivalent circuits internal components inside packaged transistor. Based analysis, optimum susceptance provided by at was obtained. proposed DPA using 45 W gallium-nitride high electron mobility transistor both...

In this letter, a circularly polarized Spidron fractal dielectric resonator antenna is presented. A wide 3-dB axial ratio (AR) bandwidth realized by merging and C-shaped slot that can produce circular polarization. The proposed excited through the coupling between in ground plane 50-Ω microstrip feeding line. prototype of fabricated tested. Reasonable agreement achieved measurement simulation. experimental results show has -10- dB reflection 37.29% (4.32-6.30 GHz) AR 11.57% (5.13-5.76 GHz)....

This paper presents a full-CMOS wireless power receiving unit (WPRU) with high-efficiency 6.78-MHz active rectifier and dc-dc converter for magnetic-resonant alliance (A4WP) applications. The proposed delay-locked loop (DLL) is highly efficient receiver circuit intended use in resonant charging applications frequency of 6.78 MHz. Each MOSFET the turned on off based ac input voltage. delay between current voltage due to delays internal blocks such as limiter, level shifter, gate driver,...

In this paper, a high efficiency dc-dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) ultralow applications. The hybrid DPWM core linearity consumption to implement the converter. It composed delay control using counter line. An adaptive window analog reduce output voltage ripple within 20 mV. A dead time generator implemented ST-ZCD minimize reverse current. can improve by...

A sidelobe-reduced, four-beam array antenna fed by a modified 4 × Butler matrix (BM) is proposed for 5G applications. Two attenuators are utilized in two external channels of the BM to realize tapered amplitude distribution. In addition, three H-slots employed as decoupling structures enhance isolation between input ports. The then cascaded with 7 microstrip comb-line establish four steering beams high gains and reduced sidelobe levels. prototype fabricated experimentally demonstrated....

This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz designed efficiently harvest RF signals and convert into useable DC voltages for energy harvesting applications. The proposed scheme employs dual-path, series (lowpower) path parallel (high-power) path, maintain high power conversion efficiency (PCE) over wide input range. dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC)...

This paper presents a Doherty power amplifier (DPA) based on asymmetric cells using an even input drive and appropriate peak fundamental current ratio (FCR) between the peaking carrier amplifier. Using output combiner for DPA, not only better load modulation but also enhanced gain can be achieved. After providing analysis currents, design guide proposed DPA FCR is presented. For verification, conventional DPAs were designed GaN-HEMTs 2.14-GHz band. downlink long-term evolution signal having...

This brief presents a three-way Doherty power amplifier (DPA) with symmetric structure in terms of the output capacities between carrier and peaking amplifiers for high efficiency linearity. Based on analysis peak at back-off, was adopted to have higher overall modulated signal. Through optimized bias condition two amplifiers, proposed DPA can be linearized wide range. To validate scheme, designed implemented using 60 W GaN-HEMT 30 GaN-HEMTs amplifiers. Using 2.14 GHz long-term evolution...

This brief presents asymmetric load matching networks for broadband Doherty power amplifiers (DPAs). The output combiner consists of two λ/4 impedance transformers with optimized characteristic values in order to provide a modulation at high level; the bandwidth limitation efficiency back-off level can be then mitigated. For proper proposed combiner, between carrier and peaking are proposed. input were designed using balanced open stubs, which more insensitive frequency than unbalanced...

In this letter, a compact single-feed circularly polarized dielectric resonator antenna is proposed for X-band applications. The radiator comprises semi-eccentric annular (DR), which semi-elliptical DR with hollow elliptical cylinder. A vertical coaxial probe located adjacent to cutting surface of the excite antenna. two main design parameters, aspect ratio and feeding position, were optimized, prototype was fabricated tested. experimental results exhibit -10-dB reflection bandwidth 29.14%...

This paper presents a high-gain multi-input low-noise amplifier (LNA) design aimed at achieving stable phase and minimal noise within flexible gain range for modern wireless communication systems. The proposed LNA, designed using CASCODE architecture implemented in 65 nm silicon-on-insulator (SOI) process, demonstrates significant improvements isolation, reduction, miniaturization. SOI process reduces parasitic capacitance, enhancing performance thermal/electrical critical high-frequency...

The design of a broadband waveguide magic-T was accomplished using genetical swarm optimization (GSO) technique. A multi-stepped, off-centered conducting cone used to enhance the bandwidth performance conventional magic-Ts. geometrical parameters stepped were optimized by GSO, and for X-band application fabricated tested. Measured scattering are shown be in good agreement with computed results. exhibits -20 dB reflection over 20.0% at all ports.

In this paper, a design algorithm for sharedaperture dual-band transmitting/receiving array antenna is proposed active radar applications. Sand X-band elements are located on single planar aperture, but the transmitting and receiving apertures separated simultaneous receiving. First, difference sets genetic (GA) used to optimize thinned arrays with radiation characteristics equivalent those of periodic array. For array, GA applied derive configurations quadratic programming utilized...

A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The modulator, based on a hybrid buck converter consisting of wideband linear and highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output (APT) low power. For the APT mode, switched off operates as normal to DC voltage according optimum switch sizes were analyzed applied each mode higher efficiency. An was designed fabricated using...

This paper presents a reconfigurable wide input power range radio frequency (RF) energy harvester (EH) with alliance for wireless (A4WP) receiver (WPR). A RF-DC converter RF EH and maximum point tracking algorithm are proposed to maintain high efficiency over -20 +20 dBm. The A4WP WPR is designed merged the receive higher than In order improve conversion (PCE), delay between ac voltage current compensated by open-loop compensation method. chip implemented in 0.18 μm...

This letter presents a dual-band (0.902 and 2.45 GHz) radio frequency (RF)-dc CMOS converter employing the internal threshold voltage cancelation (IVC) technique to harvest electromagnetic energy. The realized RF-dc maintains high power conversion efficiency (PCE) by passively reducing of forward-biased transistors so as increase harvested power, increases reverse-biased reduce leakage current. More than 20% measured PCE is achieved at 0.902 GHz from -9 10-dBm input range peak 47% obtained 1...

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through coarse counter, middle, fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle delay-locked loops (ADDLLs) is provided to ensure stability of generated slots. Charge pump, loop filter, voltage-controlled line inside conventional analog (DLLs) are...

This letter proposes a novel capacitively coupled microstrip comb-line (CCMCA) array antenna for millimeter-wave band applications. The proposed has the advantages of low profile, cost, and ease fabrication band. By adjusting gaps between radiating strips feeding line, an with sidelobe level can easily be designed. To verify suitability applications, two arrays (1 × 18 4 18) were designed developed at design frequency 79 GHz. measured results show good agreement simulated ones in terms...

This article presents a Doherty power amplifier (DPA) based on asymmetric cells with complex combining load (CCL). In this study, new and intuitive design technique using the Smith chart is proposed for developing network of CCL-DPA. The peaking consists larger cell size compared to that carrier in order achieve higher gain peak output comparison conventional CCL-DPAs symmetric cells. For verification purposes, CCL-DPA was designed implemented 6- 10-W GaN-HEMTs amplifiers, respectively....