A5029371458- Energy Harvesting in Wireless Networks
- Innovative Energy Harvesting Technologies
- Wireless Power Transfer Systems
- Analog and Mixed-Signal Circuit Design
- Advanced DC-DC Converters
- Advanced Battery Technologies Research
- Multilevel Inverters and Converters
- CCD and CMOS Imaging Sensors
- Electrowetting and Microfluidic Technologies
- Full-Duplex Wireless Communications
- Neuroscience and Neural Engineering
- RFID technology advancements
- Silicon Carbide Semiconductor Technologies
- Modular Robots and Swarm Intelligence
Sungkyunkwan University
2017-2025
In this paper, a self-threshold voltage (Vth) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold of the rectifying devices by bias generated auxiliary transistors output DC voltage. compensate PMOS device while NMOS RF-DC was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. experimental results show that design achieves better performance both...
In this paper, a low-power reconfigurable ambient Radio Frequency to Direct Current power (RF–DC) converter using an internal threshold voltage cancellation (IVC) scheme with auxiliary transistors block is presented. A maximum point tracking (MPPT) algorithm implemented in order maintain the high efficiency by automatically selecting number of stages. The proposed efficiently converts RF signals DC dynamically controlling forward and reversed-biased primary rectification body. During...
A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with front end of 6-bit Flash ADC five channels time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed shared SAR provides area efficient Time-skew calibration implemented to minimize the discrepancy between output ADC's channels. To rectify decision error extract time-skew information,...
In this paper, a power regulated circuit (PRC) is proposed for system-on-a-chip (SoC) applications. The PRC composed of limiter, bandgap reference (BGR), three low-dropout regulators (LDOs), and bias generator. A high output voltage an active rectifier given to the which limits it desired supply circuits in PRC. curvature-compensated BGR robust process, temperature (PVT) variations are designed provide stable LDOs. LDOs implemented generate dc voltages. fabricated 130 nm bipolar-CMOS-DMOS...
This article present high efficient electromagnetic energy harvesting system for low frequency applications. The proposed circuit is composed of two stages. In the first stage (EM) rectifier uses an improved structure with active diodes powered internally by a passive ac-dc positive and negative voltage quadrupler. boost input peak 0.6 V to +0.8 -0.8 power unbalance-size comparators (Comp_1 Comp_2). unbalance size comparator minimize delay introducing offset in order reverse leakage current....
This article presents a power management integrated circuit for wireless receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance (A4WP) and consortium (WPC) standards. gate charge recycling technique proposed in the so that current generated by switching of high side driver can be recycled to output voltage order enhance efficiency. step-down dc–dc converter with bootstrap dynamic pull-up resistor designed. The chip implemented 0.18-μm bipolar-CMOS...
This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the losses of rectifier, therefore, as way to reduce losses, technique is proposed. The output power 15 W achieved enable rapid charging using three standards for wireless mode, magnetic induction (WPC and PMA), resonance (A4WP). Power-sharing used lower amount consumed by each standard mode core. In WPC, PMA zero current sensing (ZCS) has been while in A4WP digitally controlled...
This work proposes a high-efficiency constant on-time (COT) control dc-dc buck converter with an adaptive gain current sensor for the power management integrated circuits. To address issues of conventional ontime method, circuit is proposed which improved system stability and efficiency. The design input voltage range 4.5 V <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 12$</tex> V, output 0.5 5\mathrm{V}$</tex> , between 10...
This paper presents a 6-parallel RF-DC Energy Harvesting (EH) Rectifier with Dickson Charge Pump Structure. The EH is used and receives total power of 3W, 500mW by each stage. parallel structure reduces the voltage that devices must withstand to avoid limiting their operation due device characteristics. Proposed RF designed an 180nm BCD process achieves maximum conversion efficiency (PCE) 85.51 percent at 3W input while delivering output DC 11.32V 50-ohm load resistance.
This work proposes a ramp generator with trimming control bits for quick response of PWM DC-DC buck converter IoT applications. Due to the addition bits, frequency 2 MHz has been achieved. The range is from 1.41 3.998 <0000> <1111>. A achieved bit <1000>. output voltage 1.2V an input 1.8 V. load current supplied between 0-200 mA. proposed designed in 180 nm CMOS process active area 200 μm X 170 μm.
This paper proposes two more advanced techniques for blocking reverse currents in an Active Rectifier. We propose Rectifier with Enhanced Accuracy Zero Current Sensing (ZCS) and Deglitch Circuit wireless power transfer system. The proposed ZCS is accurately detect input changes enhance the Power Conversion Efficiency (PCE) of Using a BCD 0.18 μm fabrication Operation frequency 150 kHz. maximum conversion efficiency 98.59 % at R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents a design of 5.8 GHz RF-DC converter for energy harvesting applications to harvest the RF from environment. To improve power conversion efficiency (PCE), proposed architecture compensates threshold voltage rectifying devices. The is designed and simulated in 130 nm Bipolar-CMOS-DMOS (BCD) technology with an active area <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$12\ \mu m\times 16\ m$</tex> . results show PCE more 20%...
This paper presents a power-up circuit design for energy harvesting applications. The two main blocks of the are bandgap reference (BGR) and low drop-out voltage regulator (LDO). A soft-start is added to stabilize output BGR LDO. To protect from noise fluctuation, employs current-mode regulator. generates fixed 1.2 V. input 4.2 V 3.3 with load current 40 mA. Power Supply rejection ratio achieved by -59.9 dB -50.5 LDO, respectively. line regulation proposed LDO 3.04 mV/V 6.8 mV/mA,...