This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz designed efficiently harvest RF signals and convert into useable DC voltages for energy harvesting applications. The proposed scheme employs dual-path, series (lowpower) path parallel (high-power) path, maintain high power conversion efficiency (PCE) over wide input range. dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC)...

This letter presents a dual-band (0.902 and 2.45 GHz) radio frequency (RF)-dc CMOS converter employing the internal threshold voltage cancelation (IVC) technique to harvest electromagnetic energy. The realized RF-dc maintains high power conversion efficiency (PCE) by passively reducing of forward-biased transistors so as increase harvested power, increases reverse-biased reduce leakage current. More than 20% measured PCE is achieved at 0.902 GHz from -9 10-dBm input range peak 47% obtained 1...

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. improved common mode charge redistribution algorithm proposed binary weighted SAR ADC. The method uses available voltage (VCM) level ADC conversion, and this reduces switching power by more than 12% without any additional DAC driver as compared to merged capacitor (MCS)....

This article presents a high-efficiency fast transient constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused sensor is proposed to enhance loop stability and improve power conversion efficiency at light load. Input sensed added feedback voltage increase output ripple voltage. Fast dc-offset cancelation technique introduced achieve...

In this paper, a self-threshold voltage (Vth) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold of the rectifying devices by bias generated auxiliary transistors output DC voltage. compensate PMOS device while NMOS RF-DC was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. experimental results show that design achieves better performance both...

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity digital-to-analog (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique proposed. The proposed consumes only 63.75 CVREF2 energy, which far less as compared to conventional without dividing or adding additional switches. In addition, bootstrap implemented ensure enhanced...

Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior a sensor is highly dependent on the temperature gradient which seriously degrades its reliability reduces measurement accuracy. In this paper, polynomial-based adaptive digital compensation presented for automotive piezoresistive applications. non-linear dependency accurately compensated by...

In this research work, a reconfigurable 2.45-GHz RF-DC converter realized in 180-nm complementary metal-oxide semiconductor (CMOS) technology is proposed to efficiently harvest electromagnetic energy. The circuit composed of low-power path rectifier, high-power and an adaptive control (APC) circuit. APC made-up comparator, two switches, inverter. senses the output voltages rectifiers generates signal automatically switch between lower-power operation depending upon RF input power level....

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and improve linearity of digital-to-analog converter (DAC). The consumes only 149 CVREF2 for 10-bit case. A rail-to-rail dynamic latch comparator implemented with adaptive control better efficiency. Additionally, optimize consumption performance logic...

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented this paper. To optimize the architecture with respect consumption and performance, several techniques are proposed. switching method which employs common mode charge recovery (CMCR) process capacitive digital-to-analog (CDAC)...

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with front end of 6-bit Flash ADC five channels time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed shared SAR provides area efficient Time-skew calibration implemented to minimize the discrepancy between output ADC's channels. To rectify decision error extract time-skew information,...

In this paper, a power regulated circuit (PRC) is proposed for system-on-a-chip (SoC) applications. The PRC composed of limiter, bandgap reference (BGR), three low-dropout regulators (LDOs), and bias generator. A high output voltage an active rectifier given to the which limits it desired supply circuits in PRC. curvature-compensated BGR robust process, temperature (PVT) variations are designed provide stable LDOs. LDOs implemented generate dc voltages. fabricated 130 nm bipolar-CMOS-DMOS...

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of structure, choppers are used every stage high gain amplifiers. Besides, required area and power, only CIC filter structure adopted as decimation filter. has configurable that can be different data rates input bandwidths. The...

In this paper, we present a low-power 10 Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) which is suitable for low power mixed signal applications especially IoT devices. We have used Class-AB type amplifier in Reference generator of SAR ADC to reduce current consumption and satisfy the linearity property better performance ADC. The proposed circuit uses CMOS 0.18 μm process technology supply voltage 5 V. ENOB 9.623 SNDR 58.688 dB with 0.44 mA.

This paper presents a 10-bit, 8 MS/s Asynchronous SAR ADC with supply voltages of 1 V for low power mixed signal applications. The proposed asynchronous consist comparator, logic block and two control blocks (positive CDAC Negative CDAC). prototype the is implemented in 55 nm CMOS process technology. It achieves ENOB 9.765 bit sampling frequency 8MS/s, input range 0.2–0.8 consumption 0.124 mW.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. dual-path bootstrap switch was to increase linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog (CDAC) switching technique...

This article presents a power management integrated circuit for wireless receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance (A4WP) and consortium (WPC) standards. gate charge recycling technique proposed in the so that current generated by switching of high side driver can be recycled to output voltage order enhance efficiency. step-down dc–dc converter with bootstrap dynamic pull-up resistor designed. The chip implemented 0.18-μm bipolar-CMOS...

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for wireless power transfer system. is four–channel SAR ADC structure with 10-bit resolution each channel, which can also be applied as single 12-bit ADC. To reduce the area and number of required devices in module, hybrid-type capacitor resistor DACs applied, DAC shared between channels determines seven least significant bits (LSB)s, while three most (MSBs). For operation mode, to...

This paper presents an ultra-low power asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with Wake-up And Sample (WAS) logic. A fully operation and WAS logic is proposed to improve the accuracy of conversion process lower overall consumption. The Asynchronous SAR ADC achieves Effective number bits (ENOB) 9.757 bit input range 0.2 V 0.8 at 8 MS/s sampling rate implemented in 65 nm CMOS technology. current consumption architecture 46 μA 1 supply.

This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the losses of rectifier, therefore, as way to reduce losses, technique is proposed. The output power 15 W achieved enable rapid charging using three standards for wireless mode, magnetic induction (WPC and PMA), resonance (A4WP). Power-sharing used lower amount consumed by each standard mode core. In WPC, PMA zero current sensing (ZCS) has been while in A4WP digitally controlled...

In this paper, a design of 14-bit digital decimation filter for transimpedance amplifier (TIA) based sensor application is presented. TIA used detecting very small variations in the current highly sensitive applications. The output digitized by high-resolution ADC. Continuous-Time sigma-delta modulator analog-to-digital converters (CT-SDM ADC) offer high resolution with CIC which reduces overall power consumption. proposed comprised three integrators, digitally controlled decimator, comb...

This paper presents low-power area efficient 8-bit 500 kS/s Coarse-Fine Resistor-String Digital to Analog Converter (CFRS-DAC). structure in the proposed DAC reduces unit resistors as compare with conventional R-string DAC. Proposed 28 % and 70 of inverted-ladder Conversional DAC, respectively. Class-B Opamp buffer is used reduce offset errors power consumption. The shows an Effective Number Bits (ENOB) 7.917 bits, Signal Noise Ratio (SNR) 49.42 dB, Spurious Free Dynamic Range (SFDR) 56.79...

In this paper, High static and dynamic performance low power 100 MSPS 10-bit segmented Current Steering DAC (CS-DAC) is presented. This proposed designed using 130nm CMOS technology for wireless communications. The architecture follows 3+3+4 segmentations, in which 6 MSB bits are realized with unary DACs, 4 LSB binary structure. To improve the performance, re-timing latches Cascoded current cell used, respectively. DAC, Spurious Free Dynamic Range (SFDR) > 78 dB signal frequency up to 33.5...