A5065792570- Energy Harvesting in Wireless Networks
- Radio Frequency Integrated Circuit Design
- Wireless Power Transfer Systems
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Innovative Energy Harvesting Technologies
- Antenna Design and Analysis
- Surface Roughness and Optical Measurements
- Electrostatic Discharge in Electronics
- Advanced Power Amplifier Design
- Full-Duplex Wireless Communications
- Electromagnetic Compatibility and Noise Suppression
- Brain Tumor Detection and Classification
- Advanced Memory and Neural Computing
- Advanced Thermoelectric Materials and Devices
- Silicon and Solar Cell Technologies
- Low-power high-performance VLSI design
- Advanced Battery Technologies Research
- CCD and CMOS Imaging Sensors
- Advanced Optical Imaging Technologies
- Industrial Vision Systems and Defect Detection
- Thin-Film Transistor Technologies
- Advanced MIMO Systems Optimization
- RFID technology advancements
Ulsan National Institute of Science and Technology
2025
Sungkyunkwan University
2021-2023
Scripps Korea Antibody Institute
2021-2023
Philips (Finland)
2005-2006
In this paper, a self-threshold voltage (Vth) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold of the rectifying devices by bias generated auxiliary transistors output DC voltage. compensate PMOS device while NMOS RF-DC was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. experimental results show that design achieves better performance both...
This paper presents an integer-N phase-locked loop (PLL) for RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with DC-DC converter, and bias-controlled charge pump feedback are proposed. The frequency range of VCO is 4.5–6.1 GHz, target proposed PLL 2.4 5.8 GHz in industry–science–medical band. It designed same phase margin bandwidth using one filter. consumes less than 8 mW from...
This paper presents a DC-DC boost converter for energy harvesting. The time-domain maximum power point tracking (MPPT) technique implements to maximize the source's harvesting performance with no additional switch and time slot. Furthermore, it is implementing digital self-tracking zero current detectors (ST-ZCD) high efficiency. fabricates 180nm CMOS process. input voltage of ranges from 0.2 0.7V generates output 1.2V. total area this MPPT operation 600 μm x 475 μm. measured conversion...
This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, satisfy required specifications. switch applies six stacks series shunt transistors as big 3.9 mm/160 nm 0.75 nm, respectively. A negative charge pump voltage booster generate boosted control voltages improve harmonics keep Inter-Modulation Distortion...
This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed synthesizable RTL-based CNN architecture this purpose. The adopted technique of parallel computation multiplication and accumulation (MAC) approach optimizes the hardware overhead significantly reducing arithmetic calculation achieves instant results. While...
This article presents a power management integrated circuit for wireless receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance (A4WP) and consortium (WPC) standards. gate charge recycling technique proposed in the so that current generated by switching of high side driver can be recycled to output voltage order enhance efficiency. step-down dc–dc converter with bootstrap dynamic pull-up resistor designed. The chip implemented 0.18-μm bipolar-CMOS...
This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) Continuous Tracking (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, need Time-to-Digital Converter (TDC) is eliminated providing CFTL circuitry. feature makes design compact, suitable IoT The based on synthesizable pulse injection frequency-locked loop along with ultra-low-power LC...
This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for diversity receive module where the application is multi-mode cellular handsets. The LB LNA covers frequency range between 617 MHz to 960 in 5 different bands Pole Single Throw (5PST) switch selects two of them are main three auxiliary bands. presented structure gain modes from -12 18 dB with 6 steps each mode has current consumption. In order achieve Figure (NF) specifications high modes, we have adopted...
A 2.6 inch VGA SOP (System On Panel) employing an advanced CMOS LTPS technology has been developed for mobile applications. Sequential analog data sampling scheme was adopted to achieve the narrow bezel comparable a-Si panel. The integrated gate driver includes dual logic structure increase products yield and display quality. applies line/block overlap driving method exclude block-dim. pixel density is over 300ppi aperture ratio about 40%.
This paper presents a 5.8 GHz differential cascode power amplifier for an over-the-air wireless transfer application. Over-the-air provides variety of benefits in several applications such as the Internet Things and medical implantation applications. The proposed PA features two fully differentially active stages with custom-designed transformer to provide single-ended output. custom-made shows high quality factor, 11.6 11.2 primary secondary sides at GHz. Fabricated using standard 180 nm...
In this paper, we propose a peak-to-average-ratio (PAPR) based simultaneous wireless information and power transfer (SWIPT) system for Internet-of-Things (IoT) sensor applications. Conventional SWIPT is on power-hungry transmitter receiver modules. The presence of such blocks directly impact the consumption in IoT devices. This problem can be solved by proposing an ultra-low-power communication mechanism. Recently with multi-tone under consideration because its increased conversion...
This paper presents a Dual-Port-15-Throw (DP15T) antenna switch module (ASM) Radio Frequency (RF) implemented by branched technique which has high linearity for wireless communications and various frequency bands, including low- band of 617-960 MHz, mid-frequency 1.4-2.2 GHz, high-frequency 2.3-2.7 GHz. To obtain an acceptable Insertion Loss (IL) provide consistent input each throw, is proposed that distributes unified magnetic field at the inputs throws. The other role to increase...
In this brief, a self-calibrated two-point delta-sigma modulation technique for CMOS RF transmitter is proposed use voltage-controlled oscillator (VCO) and delta–sigma modulator in frequency synthesizer. By using the counter to calibrate deviation of desired value, gain mismatch between two paths can be completely calibrated by modifying VCO path. The therefore guarantees robust performance against PVT variations without any additional circuit. This applied Bluetooth Low Energy (BLE)...
In the fabrication of CMOS AMLCD panel, there has been much effort to reduce number mask steps in order achieve simpler process as well low-cost production. this paper, two methods for reduction; storage and LDD self-aligned sub micron n-channel TFT are introduced with good uniformity concept.
This paper presents a digital power amplifier (DPA) with 43-dB dynamic range and 0.5-dB/step gain steps for narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in dual-band architecture both the low band high frequency coverage an NBIoT two individual paths, amplification, attenuation, to provide wide when paths are implemented. To perform fine control over steps, ten fully differential cascode cores, parallel binary sizing, used amplify enable...
This paper presents a radio frequency (RF) triple pole throw 3P3T cross antenna switch for cellular mobile devices. The negative biasing scheme was applied to improve the power-handling capability and linearity of by increasing maximum tolerable voltage drop across drain source reverse parasitic junction diodes. To avoid signal reflection through in off-state, all ports were equipped with 50-ohm termination provide pull-down path. Considering simultaneous operation different cases, presented...
In this paper, a clock frequency doubler capable of handling large variation in input duty cycle and PVT (Process, Voltage Temperature) is presented. Clock with XOR gate cannot be used if the not 50 %. A circuit that calibrates to % added front doubler, has low jitter doubles even The fully digital method proposed paper overcomes disadvantages existing analog methods, such as standby current area due use capacitors amplifiers, enable low-current, low-area implementation. reference...