Honey Durga Tiwari

ORCID: 0000-0001-6630-6246
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Research Areas
  • Advanced Wireless Communication Techniques
  • Video Coding and Compression Technologies
  • Error Correcting Code Techniques
  • Energy Harvesting in Wireless Networks
  • Advanced Vision and Imaging
  • Advanced Data Compression Techniques
  • Wireless Power Transfer Systems
  • Cooperative Communication and Network Coding
  • Innovative Energy Harvesting Technologies
  • Digital Filter Design and Implementation
  • Multimedia Communication and Technology
  • Embedded Systems and FPGA Design
  • Numerical Methods and Algorithms
  • Radio Frequency Integrated Circuit Design
  • Image and Video Quality Assessment
  • Low-power high-performance VLSI design
  • Advancements in PLL and VCO Technologies
  • Advanced Wireless Network Optimization
  • IoT-based Smart Home Systems
  • Robotics and Automated Systems
  • Cellular Automata and Applications
  • Advanced DC-DC Converters
  • Digital Image Processing Techniques
  • Coding theory and cryptography
  • Advanced Adaptive Filtering Techniques

Samil Pharm (South Korea)
2016

Sungkyunkwan University
2012-2015

Konkuk University
2008-2013

Indian Institute of Technology Madras
2006

Vedic mathematics is the name given to ancient Indian system of that was rediscovered in early twentieth century from sculptures (Vedas). It mainly deals with mathematical formulae and their application various branches mathematics. The algorithms based on conventional can be simplified even optimized by use Sutras. These methods ideas directly applied trigonometry, plain spherical geometry, conics, calculus (both differential integral), kinds. In this paper new multiplier square...

10.1109/socdc.2008.4815685 article EN International SoC Design Conference 2008-11-01

This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose capacitance-tovoltage converter circuit that measures the capacitance value of sensor high accuracy linearity. In this paper, linearity is guaranteed using full-analog an calibration circuit. The proposed design implemented CMOS 0.35 μm technology active area 1.94 mm x mm. full output range from 0.5 to 4.5 V. ratiometricity within ±0.7% when...

10.1109/jsen.2014.2369471 article EN IEEE Sensors Journal 2014-11-11

Wireless data transmission standards like 802.16e, 802.11n, employ Low Density parity Check (LDPC) codes for error control coding. The bit flipping decoding algorithms presents a tradeoff between the correcting capability, resources and time. Software based LDPC decoders provide adaptation capabilities in system parameters such as block size code rate. In real-time, low-power mobile environments, Single-Instruction Multiple-Data (SIMD) processor currently used video processing, could also be...

10.1109/tce.2011.6131118 article EN IEEE Transactions on Consumer Electronics 2011-11-01

This article presents a full-CMOS receiver for magnetic resonant wireless battery charging system. A wide-input range CMOS multi-mode active rectifier is proposed The configuration automatically changed with respect to the magnitude of input AC voltage. output voltage sensed by comparator. Furthermore, selected switches as original mode, one-stage multiplier or two-stage mode. As result, rectified DC from 7.5 19 V an 5–20 V. chip implemented using 0.35 μm BCD technology area around 5 × 2.5...

10.1080/00207217.2014.896419 article EN International Journal of Electronics 2014-02-24

The conventional OFDM system employs the IFFT-FFT structure to impart orthogonolity feature. However, due complex nature of FFT, implementation size is large enough. can also be provided if IDCT-DCT used in place FFT. This will reduce area and increase computation speed as only real calculations are required. In this paper we present DCT based system. prevalent H.264 standard taken into reference it has faster operation compared structure. DCT-IDCT was done on ALTERA CYCLONE -II FPGA....

10.1109/socdc.2008.4815679 article EN International SoC Design Conference 2008-11-01

Low-density parity check (LDPC) codes have gained much attention due to their use of various belief-propagation (BP) decoding algorithms impart excellent error-correcting capability. The BP decoders are quite simple; however, computation-intensive and repetitive process prohibits in energy-sensitive applications such as sensor networks. Bit flipping-based algorithms, especially implementation-efficient, reliability ratio-based, weighted bit-flipping (IRRWBF) decoding; shown an tradeoff...

10.1109/tpds.2012.54 article EN IEEE Transactions on Parallel and Distributed Systems 2012-02-07

As compared to other wireless transfer mechanism, like the inductive coupling method, magnetic resonance-based power can achieve over a larger distance. However, as transmission range increases, change in load impedance lowers efficiency currently available transmitters. This article presents CMOS transmitter for resonant battery charging system. A class-E amplifier (PA) with an automatic control loop and compensation circuit is proposed improve efficiency. The transmitted controlled by...

10.1080/00207217.2014.880991 article EN International Journal of Electronics Letters 2014-01-30

In this article, we present the implementation of high throughput two-dimensional (2-D) 8 × forward and inverse integer DCT transform for H.264. Using matrix decomposition operation, such as Kronecker product direct sum, can be represented using simple addition operations. The dual clocked pipelined structure proposed uses non-floating point adders does not require any transpose memory. Hardware synthesis shows that maximum operating frequency architecture is 1.31 GHz, which achieves 21.05...

10.1080/00207217.2012.731371 article EN International Journal of Electronics 2013-01-30

In the paper we propose a 4 × 2-D DCT transpose architecture for use in H.264 video coding standard. Using matrix decomposition entire can be made parallel nature such that resulting circuit is purely combinational. The values then computed almost one clock cycle. As computation independent of data clock. actual maximum operating frequency and throughput design much higher than input rate. reversible helps to IDCT calculation without change design. FPGA implementation proposed shows 4.76...

10.1109/socdc.2008.4815642 article EN International SoC Design Conference 2008-11-01

Vedic mathematics is the name given to ancient Indian system of that was rediscovered in early twentieth century from sculptures (Vedas). It mainly deals with mathematical formulae and their application various branches mathematics. The algorithms based on conventional can be simplified even optimized by use Sutras. These methods ideas directly applied trigonometry, plain spherical geometry, conics, calculus (both differential integral), kinds. In this paper, new multiplier square...

10.1109/icaccs.2019.8728430 article EN 2019-03-01

As compared to other wireless transfer mechanism, like the inductive coupling method, magnetic resonance-based power can achieve over a larger distance. However, as transmission range increases, change in load impedance lowers efficiency currently available transmitters. This article presents CMOS transmitter for resonant battery charging system. A class-E amplifier (PA) with an automatic control loop and compensation circuit is proposed improve efficiency. The transmitted controlled by...

10.1080/00207217.2014.881559 article EN International Journal of Electronics 2014-01-13

This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the resistances. The is composed of 4-stages and its configuration automatically changes based on required voltage level. In order to keep over internal blocks are activated or deactivated by clock driver in minimizing switching loss due On Off operations MOSFET. addition, leakage current paths each mode blocked compensate variation respect range. chip fabricated using 0.18...

10.5573/jsts.2014.14.6.777 article EN JSTS Journal of Semiconductor Technology and Science 2014-12-30

10.1016/j.dsp.2012.04.014 article EN Digital Signal Processing 2012-04-27
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