A5002874074- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Magnetic properties of thin films
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Evolutionary Algorithms and Applications
- VLSI and FPGA Design Techniques
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Quantum and electron transport phenomena
- Analog and Mixed-Signal Circuit Design
- Network Packet Processing and Optimization
- Music Technology and Sound Studies
- Neural Networks and Applications
- Music and Audio Processing
- Machine Learning and ELM
- Energy Harvesting in Wireless Networks
- Magnetic Field Sensors Techniques
- Metaheuristic Optimization Algorithms Research
- Speech and Audio Processing
- Quantum-Dot Cellular Automata
- Advanced Battery Technologies Research
- Interconnection Networks and Systems
Tohoku University
2016-2025
Spintronics Research Network of Japan
2012-2020
MediaTek (China)
2019
Tokyo Institute of Technology
2019
Fujitsu (Japan)
2019
Tohoku University Hospital
2017
Tohoku Institute of Technology
2015
NEC (Japan)
2014
Systems Research Institute
2009
Toyohashi University of Technology
2006-2008
Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs embedded that can be used in conventional VLSI circuits systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages devices, especially magnetic tunnel junction (MTJ) circuits, are discussed, current...
For the first time, we demonstrated 55 nmCMOS/ spin-orbit-torque-device hybrid magnetic randomaccess memory (SOT-MRAM) cell with field free writing. writing, developed canted SOT device under 300 mm BEOL process full compatible 400°C thermal tolerance. Moreover, its advanced as follows; channel layer PVD for high spin Hall angle tolerance, low damage RIE technology of MTJ TMR/thermal stability factor (Δ) and ultra-smooth surface metal via to reduce contact resistance. By above technologies,...
Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming serious power-consumption problem that rapidly become dominant constraint on performance improvement today's VLSI processors. Normally-off and instant-on capabilities with small area penalty due to non-volatility three-dimensional-stackability MTJ in above structure allow us apply power-gating technique fine...
A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted dissipation. The proposed nonvolatile designed by establishing an automated design environment MTJ-based logic-circuit IPs and peripheral assistant tools, as well precise MTJ device model produced the test chips. Through measurement...
A cost-efficient self-terminated write driver is proposed for low-energy RAM and logic circuits by using spin-transfer-torque (STT)-magnetic tunnel junction (MTJ) devices. Since a bidirectional current required STT switching, data-dependent write-completion monitoring, where the node with large voltage difference between before after switching selectively used, makes it possible to achieve sufficiently sense margin at any directions. By enhancement of margin, monitoring...
The demand for energy-efficient, high-performance microcontroller units (MCUs) the use in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a substantial increase. In response, research concerning development of several low-power-consuming MCUs been actively pursued. performance level such MCUs, however, not sufficient, thereby rendering them non-feasible IoT that process large number received signals immediately followed by extraction valuable information...
A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ make it possible not only to reduce the effect resistance variation, but also enhance programmability values, which achieves sufficient sensing margin even when process variation serious in recent nanometer-scaled VLSI....
The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) become technology platform to overcome the issue in power consumption logic for application from IoT AI; however, STT-MRAM a tradeoff relationship between endurance, retention, and time. This is because MTJ device used two-terminal device, excessive read current high-speed readout can cause unexpected data writing,...
A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to storage devices. also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components shared among all devices by logic-in-memory structure, effective area...
We propose a design optimization flow for high-speed and low-power operational transconductance amplifier (OTA) using gm/ID lookup table methodology in scaled CMOS. This advantages from as primary parameter to consider all operation regions including strong, moderate, weak inversion regions, enables the lowest power design. SPICE-based approach is employed optimize region specified by with sufficient accuracy short-channel transistors. The optimized features 1) proposal of worst-case...
In this paper, we propose a systematic intrusion detection algorithm based on time-series feature extraction for an in-vehicle network. Since packet-type valid data are transmitted inside network periodically, illegal due to unauthorized attack can be easily and uniformly detected by using periodical of data, where recurrent neural is key tool efficiently extract their feature. fact, through evaluation acquired from actual vehicles, show that the proposed method detect typical patterns such...
A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to storage devices. also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components shared among all devices by logic-in-memory structure, effective area...
A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-addressable memory (TCAM). Since critical path switching in the TCAM circuit, which determines performance of TCAM, only single MOS transistor, delay word minimized. As result, 270 ps 144-bit achieved under 90 nm CMOS/MTJ technology with magneto-resistance ratio 100%, about two times faster than conventional CMOS-based TCAM.
Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) TCAM cell circuit with high-speed accessibility. Since critical path for switching in the is only single metal-oxide-semiconductor (MOS) transistor, delay of word minimized. As result, worst-case 0.22 ns achieved 144-bit under 90 nm complementary MOS (CMOS)/MTJ technology, which about 2.6 times faster than that conventional CMOS-based...
Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) TCAM cell circuit with high-speed accessibility. Since critical path for switching in the is only single metal-oxide-semiconductor (MOS) transistor, delay of word minimized. As result, worst-case 0.22 ns achieved 144-bit under 90 nm complementary MOS (CMOS)/MTJ technology, which about 2.6 times faster than that conventional CMOS-based...
A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 × 20 2D-array is fabricated by 90nm CMOS and 70nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal are still remained the MTJ devices even when power supply cut off, standby dissipation completely eliminated utilizing tile-level gating. Power reduction further accelerated skipping wasted write operations of flip-flops (NVFFs) for...
Abstract Logic gates using magnetic tunnel junction (MTJ)-based nonvolatile logic-in-memory (NV-LIM) architecture are designed for quantized neural networks (QNNs) Internet-of-Things applications. The NV-LIM-based implementation reduces data transfer costs between storage and logic gate components, thereby greatly enhancing the energy efficiency of inference operations in QNNs. impact proposed binary ternary on consumption, delay, area overhead reduction is demonstrated through circuit...
A single-ended circuit using three-terminal magnetic tunnel junction (3T-MTJ) devices is proposed for a compact nonvolatile lookup-table (NV-LUT) circuit. The use of 3T-MTJ makes high magneto-resistance ratio used in the circuit, because read-current path separated from write-current path. By utilizing structure, NV-LUT becomes quite simple without reference In fact, effective area 6-input only 29% size corresponding CMOS-based implementation two-terminal-MTJ-based static random access...
A nonvolatile logic gate based on magnetic tunnel junction-based logic-in-memory (NV-LIM) architecture is designed for the implementation of compact and low-power binary neural network (BNN) hardware. The use NV-LIM designing BNN hardware makes it possible to reduce both computational data transfer costs associated with inference functions deep networks. Through an experimental evaluation a basic component architecture, we demonstrate that optimized its quantitative analysis can circuit area...
We demonstrate an SOT-MRAM, a nonvolatile memory using spin-orbit-torque (SOT) devices that have read-disturbance-free characteristic. The SOT-MRAM fabricated by 55-nm CMOS process achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under magnetic-field-free condition. is also implemented in dual-port configuration utilizing three-terminal structure of the device, which realizes wide bandwidth applicable to high-speed applications.