A5100623529- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Semiconductor materials and interfaces
- Advanced Memory and Neural Computing
- Nanowire Synthesis and Applications
- Ferroelectric and Negative Capacitance Devices
- ZnO doping and properties
- Thin-Film Transistor Technologies
- VLSI and Analog Circuit Testing
- Silicon and Solar Cell Technologies
- Gas Sensing Nanomaterials and Sensors
- Non-Invasive Vital Sign Monitoring
- Electrostatic Discharge in Electronics
- Semiconductor Lasers and Optical Devices
- Copper Interconnects and Reliability
- Metal and Thin Film Mechanics
- Quantum and electron transport phenomena
- Plasma Diagnostics and Applications
- Smart Materials for Construction
- Cardiovascular Health and Disease Prevention
- Antenna Design and Analysis
- Advanced Fiber Optic Sensors
- Ferroelectric and Piezoelectric Materials
Kansai University
2014-2024
Tokyo University of Science
1995-2024
Sidney Kimmel Cancer Center
2024
Thomas Jefferson University
2024
Ryukoku University
2023
Kindai University
2023
Warsaw University of Technology
2023
Osaka Institute of Technology
2023
ORCID
2016
Tohoku University
2014
This paper simulates the transport characteristics of ultrathin silicon-on-insulator MOSFETs, and evaluates influence quantum-mechanical mechanism on short-channel effects basis density-gradient model. It is clearly shown that suppresses buried-insulator-induced barrier lowering with regard to subthreshold swing because surface dark space yields a high-field region in source adjacent channel. also suggested enhances impact apparent charge-sharing effect threshold voltage effectively...
This paper discusses the role of trap-assisted-tunneling process in controlling ON- and OFF-state current levels its impacts on current-voltage characteristics a tunnel field-effect transistor. Significant high-density traps source region are observed that discussed detail. With regard to recent studies isoelectronic traps, it has been discovered deep level density must be minimized suppress leakage current, as is well known, whereas shallow can utilized control ON-state level. A possible...
This paper demonstrates and discusses the roles of hole injection from silicon substrate inclusion sub-oxide metallic Si atoms in repeatable resistance switching sputter-deposited oxide films. The not only but also atoms, are investigated detail. In addition, we show how structure interface between conductive filaments low-resistance state surrounding film influences achievement switching.
In this study, the important roles of chemical stoichiometry and hot electrons in realizing stable bipolar resistive transition sputter-deposited silicon oxide films were demonstrated. It was also clearly demonstrated that injection "hot" from substrate induces transitions for a low concentration suboxide metallic Si atoms, "cold" does not induce spite inclusion atoms films. However, it shown specific metal top electrode react with oxygen ions is useful as electron injector temporal oxygen-ion pocket
A topology optimization method can be used to find out the optical waveguide structures which have desired transmission characteristics. Using function expansion method, we avoid problem of a gray area, means that some areas having intermediate refractive index between those usable materials appear in design region. However, so far, has mainly been studied for consisting two isotropic materials. In this paper, study applicability include three or more materials, and demonstrate optimal crossing.
The paper describes the impact of pseudo-MOS technique on threshold and flatband voltages, why voltages depend silicon-on-insulator (SOI) layer thickness. Our measurements simulations suggest that band-offset-induced depletion beneath source contact obstructs local formation inversion at SOI/buried oxide interface; this effect becomes significant when SOI thickness is reduced. dependence voltage analyzed in a similar manner. temperature also addressed.
A design method giving high efficiency and low sidelobes is discussed for large aperture offset reflector antennas. new shaping technique using the subreflector beam waveguide with parabolic main proposed to simplify manufacturing process. The effectiveness of confirmed by model experiments. One problem this that edge level cannot be controlled independently level. By investigating relation between gain reduction level, which affects wide-angle sidelobe levels, realizable characteristics...
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and resistance NiSi technique, enhanced by a slit under the slim Young's modulus (YM) offset spacer covered with dual stress liner (DSL), used electron hole mobility enhancement parasitic (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sd</sub> ) reduction. The junction profile was also carefully optimized leakage...
This paper investigates the electronic structures of sputter-deposition SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> films in low-resistance state and high-resistance at room temperature low temperature. The structure post-resistive transition is also characterized spectroscopically by means current fluctuation.
This paper proposes a detailed equivalent circuit of the pseudo-MOS capacitor structure and subjects it to impedance spectroscopy. We find, using Cole–Cole plots, that three resistance components, which correspond interface traps, contact resistance, bulk traps created near contact, are observed in measurements silicon-on-insulator wafer. The simulation results gained from proposed here well match measurement over wide frequency range examined.
600V-class superjunction (SJ)-MOSFETs were developed using our original high-resolution Scanning Spread Resistance Microscopy (SSRM) analysis technology [1] for optimization of trench filling process the first time. The SSRM is a powerful tool SJ structure design, because it can be achieved measurement two- dimensional (2D)-carrier profile and detect minute voids. measured was applicable device simulation SJ-Diode estimated breakdown voltage in good agreement with experimental values. By...
We use the semi-microscopic theory to elucidate effective diffusion coefficient of carriers in one-dimensional Si wire devices. In theoretical model, it is assumed that primary spectrum process majority and minority rules process; a statistical assessment performed using quantum-mechanical analysis. Here model assumes thermalization carrier transport ruled by specific characteristic length. The reveals drastically decreases as width enters sub-10-nm range. Although suggested behavior such...
We propose new methods to control the work function (WF) of nickel-fully-silicided (Ni-FUSI) gates. clarified amounts segregated dopants, status at dielectric surface, and composition NiSi determine WF demonstrated segregation mechanism for n- p-type dopants during silicidation processes. The amount used is effective achieving wide-range WF. Nitridation gate oxide surface impacts both gates reliability. Ni content also changes These can be simultaneously WFs. Based on these three origins, we...
This paper uses various experimental results to discuss possible chemical processes in the resistance switching of sputter-deposited silicon oxide films. It is clearly demonstrated that power dissipated during transition from low state high sensitive compliance current level at initial forming. Aspects are categorized by law level, suggesting likely physics associated with process. Regarding transition, critical energy for suggests feasibility very low-switching-energy density (∼10−15 J/μm2)...
An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting structure. Applying this technique to development of 40-nm CMOS technology, failure with about ten times larger than normal via could be efficiently detected and located.
In this paper, we describe the physics-based determination of carrier effective mass assumed in a density gradient model (DGM). We show that conventional DGM corresponds to along quantization direction Schrödinger–Poisson (SP) solver, and produces good quantum correction for system with smooth conduction band bottom profile. Assuming an abrupt jump profile heterostructure system, parameters is required obtain agreement SP solver result. Whether physical meaning holds examined two-fluid...
This paper proposes theoretical models for the low-frequency noise behaviors of buried-channel SOI MOSFETs in subthreshold bias range. The model suggests that interface traps near top surface layer strongly modulate current fluctuation buried channel.
This article reports the influence of both contact condition and island edge on electrical characteristics pseudo-metal-oxide-semiconductor-field-effect-transistor (pseudo-MOSFET) method. Our measurements reveal sensitivity classical pseudo-MOSFET method condition. We clarify that presence OFF-state (an characteristic) is controlled by modulating surface silicon insulator wafer via chemical treatment. The Kelvin reveals condition, which impacts barrier height for each carrier, can determine...
Influence of native oxide growth on the top and/or back surface(s) pseudo-MOS structure impedance is analyzed. This analysis reveals a definite reduction in resistance achieved with removal surface by HF cleaning. The increased time spent after treatment. These suggest will induce erroneous estimations carrier density when attempting to use extract universal effective mobility.