L. Cecconi
A5024075553- CCD and CMOS Imaging Sensors
- Particle Detector Development and Performance
- Radiation Detection and Scintillator Technologies
- Thin-Film Transistor Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Electron and X-Ray Spectroscopy Techniques
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
- Silicon and Solar Cell Technologies
University of Geneva
2024
European Organization for Nuclear Research
2022-2024
Leibniz Institute for High Performance Microelectronics
2024
Abstract The time resolution of the second monolithic silicon pixel prototype produced for MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. ASIC contains matrix hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers 50 thick epilayer resistivity 350 Ωcm were used to produce fully depleted sensor. At highest power density tested 2.7 W/cm 2 , laser pulses found be 45 ps signals generated 1200 electrons, 3...
Abstract A monolithic silicon pixel ASIC prototype, produced in 2024 as part of the Horizon 2020 MONOLITH ERC Advanced project, was tested with a 120 GeV/c pion beam. The features matrix hexagonal pixels 100 μm pitch, read by low-noise, high-speed front-end electronics built using 130 nm SiGe BiCMOS technology. It includes PicoAD sensor, which employs continuous, deep PN junction to generate avalanche gain. Data were taken across power densities from 0.05 2.6 W/cm 2 and sensor bias voltages...
This paper presents the design of a front-end circuit for monolithic active pixel sensors. The operates with sensor featuring small, low-capacitance (< 2 fF) collection electrode and is integrated in DPTS chip, proof-of-principle prototype 1.5 mm × including matrix 32 pixels pitch 15 μm. chip implemented 65 nm imaging technology from Tower Partners Semiconductor Co. foundry was developed framework EP-R&D program at CERN to explore this particle detection. has an area 42 μm <sup...
Abstract A series of monolithic active pixel sensor prototypes (APTS chips) were manufactured in the TPSCo 65 nm CMOS imaging process framework CERN-EP R&D on sensors and ALICE ITS3 upgrade project. Each APTS chip contains a 4 × matrix with fast analog outputs buffered to individual pads. To explore characteristics, various pitches (10 µm–25 µm), geometries reverse biasing schemes included. Prototypes are fully functional detailed characterization ongoing. The design will be presented...
Abstract The MOnolithic Stitched Sensor (MOSS) is a development prototype chip towards the ITS3 vertexing detector for ALICE experiment at LHC. Designed using 65 nm CMOS Imaging technology, it aims profiting from stitching technique to construct single-die monolithic pixel of 1.4 cm × 26 cm. MOSS one prototypes developed within CERN-EP R&D framework learn how make stitched wafer-scale sensors with satisfactory yield. This contribution will describe some design challenges sensor and...
Abstract The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in framework of CERN-EP R&D on sensors and ALICE ITS3 upgrade. It features 32 × binary matrix at 15 μm pitch with event-driven readout, GHz range time-encoded digital signals including Time-Over-Threshold. proved fully functional efficient testbeam allowing early verification complete readout chain. This paper focuses design, particular its...
Abstract Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within framework Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence 1 × 10 16 n eq /cm 2 , and then tested using beam 120 GeV/c pions. The contains matrix 100 μ m pitch hexagonal pixels, read out by low noise very fast frontend electronics 130 nm SiGe BiCMOS technology process. dependence on proton efficiency time resolution this was measured operated at power density...
The time resolution of the second monolithic silicon pixel prototype produced for MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. ASIC contains matrix hexagonal pixels with 100 {\mu}m pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers 50 thick epilayer resistivity 350 {\Omega}cm were used to produce fully depleted sensor. At highest power density tested 2.7 W/cm2, laser pulses found be 45 ps signals generated 1200 electrons, 3...
Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within framework Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence 1 x 1016 neq/cm2, and then tested using beam 120 GeV/c pions. The contains matrix 100 \mu m pitch hexagonal pixels, readout out by low noise very fast frontend electronics 130 nm SiGe BiCMOS technology process. dependence on proton efficiency time resolution this was measured operated at power density between...
A monolithic silicon pixel ASIC prototype, produced in 2024 as part of the Horizon 2020 MONOLITH ERC Advanced project, was tested with a 120 GeV/c pion beam. The features matrix hexagonal pixels 100 \mu m pitch, read by low-noise, high-speed front-end electronics built using 130 nm SiGe BiCMOS technology. It includes PicoAD sensor, which employs continuous, deep PN junction to generate avalanche gain. Data were taken across power densities from 0.05 2.6 W/cm2 and sensor bias voltages 90 180...
This work presents the design of a front-end circuit optimized for monolithic active pixel sensor with small, low-capacitance collection electrode. was carried out in framework CERN-EP R&D on sensors and ALICE ITS3 upgrade first exploration TowerJazz Panasonic Semiconductor (TPSCo) 65 nm imaging technology. The integrated into 1.5 mm × proof-of-principle prototype, Digital Pixel Test Structure or DPTS, featuring sensitive area 32 pixels 15 μm pitch. occupies an ~ 42 <sup...