This paper introduces MCAST: a model compiler - based on abstract syntax trees that reads compact device models described in high-level languages VHDL-AMS/Verilog-AMS and automatically generates the simulator code C can be directly linked with existing circuit simulators such as SPICE3. We report, for first time, successful implementation of industry-grade models, including EKV, BSIM, BSIM-SOI, VHDL-AMS/Verilog-AMS. For set industry test circuits, MCAST yields exactly same simulation results...

In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated flow, and associated tools, are presented for 3D implementations of class interconnect-heavy application-specific very large-scale integrated circuits. system is first partitioned synthesized using 2D tools to set supercells with the same height varying widths. With this, reduced supercell placement 3D-via assignment. A congestion-driven simulated-annealing method used find minimize total wire...

In the digital era, influence of online media on distance education is increasing, and students' choice different determines level teaching services. A questionnaire survey was conducted 2106 students Guangxi Open University. By comparing new m

In this paper, we apply C-slow retiming and asynchronous deep pipelining to maximize the throughput-area efficiency of fully parallel low-density-parity-check (LDPC) decoding. Pipelined decoders are implemented in a 0.18 mum FDSOI CMOS process. Experimental results show that our technique is an efficient approach maximizing LDPC decoding throughput while minimizing area consumption. First, pipelined can achieve extraordinary high which non-pipelined design cannot. Second, for same...

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18μm depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D with about 8M transistors was simulated to have high throughput of 2Gb/s low power consumption only 430mW 6.4μm by 6.3μm die area. implementation is estimated offer more than 10x power-delay-area product improvement over its corresponding 2D...

Technological progress has brought about significant changes in education, and the development of intelligent speech systems provided a new technical support broader resource platform for teaching evaluating college English speaking. Evaluation is basis optimizing English-speaking instruction (ESI); this paper explores influencing factors ESI their relationship through PLS-SEM. Students’ course cognition, learning behavior, knowledge mastery, teacher-student communication have positive with...

Describes rapid implementation of semiconductor device models in SPICE using an MCAST compact model compiler. Device-model development is a vital component circuit design and traditionally very challenging task. To overcome this challenge, it would be beneficial for developers to use high-level behavioral language compilers. Implementations MOS level-3 BSIMSOI have demonstrated that modeling approach more efficient practical than traditional C/FORTRAN methodologies could save future...

VHDL-AMS and Verilog-AMS are behavioral languages extended from widely used VHDL/Verilog for analog mixed-signal applications. By describing models in the language VHDL-AMS/Verilog-AMS then compiling them with a model compiler such as MCAST, we have successfully implemented industry-grade device (including BSIM, BSIMSOI) rapidly low cost, which was previously tough high cost work. The implementation first time demonstrated capability advantages of this new method compared to traditional...

Abstract In this work, the problem of teaching English in colleges and universities throughout information age is addressed by using augmented reality (AR) technology to finish designing activities objectives. It establishes evaluation index system, uses Hummingbird optimization algorithm optimize convolutional neural network’s parameters, builds quality model based on optimization. We assess students’ happiness their capacity for autonomous learning instruction era statistical analysis, we...

Accurate prediction of low-frequency sky-wave has significance for the lower ionosphere detection and remote navigation timing. The characteristics propagation time delay in Earth-ionosphere waveguide are studied this paper based on traditional wave-hop theory FDTD method. Time variations 100 kHz one-hop sky waves given under homogeneous/exponentially graded isotropic models. great-circle distance between transmitter receiver is within 200 km. Together with a sky- ground-wave separation...

By measuring the GPS antenna pattern, based on minimum variance distortionless response adaptive beamforming principle, An easy method to suppress mutual coupling between array elements and amplitude phase errors was presented in this paper effectiveness of proposed algorithm validated a four-element linear equispaced circular simulation results show performance method.

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18 mum depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC was with about 8M transistors, placed three tiers, each one active layer metal layers, 6.9 mm by 7.0 of die area. It simulated to have 2 Gbps throughput, consume only 260 mW. This first large-scale 3D application-specific integrated circuit (ASIC)...

A new, efficient, and reliable approach to speeding up large-scale mixed signal circuit simulation is proposed for full-chip electrical statistical analysis. This has been verified with an industry 4 GHz/6-bit ADC/DAC/DEMUX ASIC design. The key idea retain at the transistor level those devices that need be modelled statistically their surrounding circuitry replace other parts of by analog behavioral models. Instead using unproven VHDL-AMS or Verilog-A simulators not optimized analysis, a...